--- zzzz-none-000/linux-3.10.107/arch/microblaze/kernel/intc.c 2017-06-27 09:49:32.000000000 +0000 +++ scorpion-7490-727/linux-3.10.107/arch/microblaze/kernel/intc.c 2021-02-04 17:41:59.000000000 +0000 @@ -1,5 +1,6 @@ /* - * Copyright (C) 2007-2009 Michal Simek + * Copyright (C) 2007-2013 Michal Simek + * Copyright (C) 2012-2013 Xilinx, Inc. * Copyright (C) 2007-2009 PetaLogix * Copyright (C) 2006 Atmark Techno, Inc. * @@ -8,23 +9,14 @@ * for more details. */ -#include #include #include -#include +#include +#include #include #include -#include -#include - -#ifdef CONFIG_SELFMOD_INTC -#include -#define INTC_BASE BARRIER_BASE_ADDR -#else -static unsigned int intc_baseaddr; -#define INTC_BASE intc_baseaddr -#endif +static void __iomem *intc_baseaddr; /* No one else should require these constants, so define them locally here. */ #define ISR 0x00 /* Interrupt Status Register */ @@ -39,6 +31,29 @@ #define MER_ME (1<<0) #define MER_HIE (1<<1) +static unsigned int (*read_fn)(void __iomem *); +static void (*write_fn)(u32, void __iomem *); + +static void intc_write32(u32 val, void __iomem *addr) +{ + iowrite32(val, addr); +} + +static unsigned int intc_read32(void __iomem *addr) +{ + return ioread32(addr); +} + +static void intc_write32_be(u32 val, void __iomem *addr) +{ + iowrite32be(val, addr); +} + +static unsigned int intc_read32_be(void __iomem *addr) +{ + return ioread32be(addr); +} + static void intc_enable_or_unmask(struct irq_data *d) { unsigned long mask = 1 << d->hwirq; @@ -50,21 +65,21 @@ * acks the irq before calling the interrupt handler */ if (irqd_is_level_type(d)) - out_be32(INTC_BASE + IAR, mask); + write_fn(mask, intc_baseaddr + IAR); - out_be32(INTC_BASE + SIE, mask); + write_fn(mask, intc_baseaddr + SIE); } static void intc_disable_or_mask(struct irq_data *d) { pr_debug("disable: %ld\n", d->hwirq); - out_be32(INTC_BASE + CIE, 1 << d->hwirq); + write_fn(1 << d->hwirq, intc_baseaddr + CIE); } static void intc_ack(struct irq_data *d) { pr_debug("ack: %ld\n", d->hwirq); - out_be32(INTC_BASE + IAR, 1 << d->hwirq); + write_fn(1 << d->hwirq, intc_baseaddr + IAR); } static void intc_mask_ack(struct irq_data *d) @@ -72,8 +87,8 @@ unsigned long mask = 1 << d->hwirq; pr_debug("disable_and_ack: %ld\n", d->hwirq); - out_be32(INTC_BASE + CIE, mask); - out_be32(INTC_BASE + IAR, mask); + write_fn(mask, intc_baseaddr + CIE); + write_fn(mask, intc_baseaddr + IAR); } static struct irq_chip intc_dev = { @@ -90,7 +105,7 @@ { unsigned int hwirq, irq = -1; - hwirq = in_be32(INTC_BASE + IVR); + hwirq = read_fn(intc_baseaddr + IVR); if (hwirq != -1U) irq = irq_find_mapping(root_domain, hwirq); @@ -120,52 +135,52 @@ .map = xintc_map, }; -void __init init_IRQ(void) +static int __init xilinx_intc_of_init(struct device_node *intc, + struct device_node *parent) { u32 nr_irq, intr_mask; - struct device_node *intc = NULL; -#ifdef CONFIG_SELFMOD_INTC - unsigned int intc_baseaddr = 0; - static int arr_func[] = { - (int)&get_irq, - (int)&intc_enable_or_unmask, - (int)&intc_disable_or_mask, - (int)&intc_mask_ack, - (int)&intc_ack, - (int)&intc_end, - 0 - }; -#endif - intc = of_find_compatible_node(NULL, NULL, "xlnx,xps-intc-1.00.a"); - BUG_ON(!intc); - - intc_baseaddr = be32_to_cpup(of_get_property(intc, "reg", NULL)); - intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE); - nr_irq = be32_to_cpup(of_get_property(intc, - "xlnx,num-intr-inputs", NULL)); - - intr_mask = - be32_to_cpup(of_get_property(intc, "xlnx,kind-of-intr", NULL)); - if (intr_mask > (u32)((1ULL << nr_irq) - 1)) - pr_info(" ERROR: Mismatch in kind-of-intr param\n"); - -#ifdef CONFIG_SELFMOD_INTC - selfmod_function((int *) arr_func, intc_baseaddr); -#endif - pr_info("%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n", - intc->name, intc_baseaddr, nr_irq, intr_mask); + int ret; + + intc_baseaddr = of_iomap(intc, 0); + BUG_ON(!intc_baseaddr); + + ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq); + if (ret < 0) { + pr_err("%s: unable to read xlnx,num-intr-inputs\n", __func__); + return ret; + } + + ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &intr_mask); + if (ret < 0) { + pr_err("%s: unable to read xlnx,kind-of-intr\n", __func__); + return ret; + } + + if (intr_mask >> nr_irq) + pr_warn("%s: mismatch in kind-of-intr param\n", __func__); + + pr_info("%s: num_irq=%d, edge=0x%x\n", + intc->full_name, nr_irq, intr_mask); + + write_fn = intc_write32; + read_fn = intc_read32; /* * Disable all external interrupts until they are * explicity requested. */ - out_be32(intc_baseaddr + IER, 0); + write_fn(0, intc_baseaddr + IER); /* Acknowledge any pending interrupts just in case. */ - out_be32(intc_baseaddr + IAR, 0xffffffff); + write_fn(0xffffffff, intc_baseaddr + IAR); /* Turn on the Master Enable. */ - out_be32(intc_baseaddr + MER, MER_HIE | MER_ME); + write_fn(MER_HIE | MER_ME, intc_baseaddr + MER); + if (!(read_fn(intc_baseaddr + MER) & (MER_HIE | MER_ME))) { + write_fn = intc_write32_be; + read_fn = intc_read32_be; + write_fn(MER_HIE | MER_ME, intc_baseaddr + MER); + } /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm * lazy and Michal can clean it up to something nicer when he tests @@ -174,4 +189,8 @@ (void *)intr_mask); irq_set_default_host(root_domain); + + return 0; } + +IRQCHIP_DECLARE(xilinx_intc, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);