--- zzzz-none-000/linux-3.10.107/arch/mips/ath79/common.c	2017-06-27 09:49:32.000000000 +0000
+++ scorpion-7490-727/linux-3.10.107/arch/mips/ath79/common.c	2021-02-04 17:41:59.000000000 +0000
@@ -21,7 +21,20 @@
 #include <asm/mach-ath79/ar71xx_regs.h>
 #include "common.h"
 
+/* == AVM/JTR JZ-57519 Move WMAC_GLUE_CAUSE_REG into sticky reg for debugging == */
+#if defined(CONFIG_SOC_AR934X) || defined(CONFIG_SOC_QCA953X)
+#include <asm/mach-ath79/avm_atheros.h>
+
+#define ATH79_RESET_STICKY_REG ((void *) KSEG1ADDR(ATH_RESET_BASE + ATH_RESET))
+#if defined(CONFIG_SOC_AR934X)
+#define WMAC_GLUE_SYNC_CAUSE_REG ((void *) KSEG1ADDR(0x18104010))
+#elif defined(CONFIG_SOC_QCA953X)
+#define WMAC_GLUE_SYNC_CAUSE_REG ((void *) KSEG1ADDR(0x18104028))
+#endif
+#endif /* defined(CONFIG_SOC_AR934X) || defined(CONFIG_SOC_QCA953X) */
+
 static DEFINE_SPINLOCK(ath79_device_reset_lock);
+static DEFINE_MUTEX(ath79_flash_mutex);
 
 u32 ath79_cpu_freq;
 EXPORT_SYMBOL_GPL(ath79_cpu_freq);
@@ -33,21 +46,53 @@
 EXPORT_SYMBOL_GPL(ath79_ddr_freq);
 
 enum ath79_soc_type ath79_soc;
+EXPORT_SYMBOL_GPL(ath79_soc);
 unsigned int ath79_soc_rev;
 
 void __iomem *ath79_pll_base;
 void __iomem *ath79_reset_base;
 EXPORT_SYMBOL_GPL(ath79_reset_base);
-void __iomem *ath79_ddr_base;
+static void __iomem *ath79_ddr_base;
+static void __iomem *ath79_ddr_wb_flush_base;
+static void __iomem *ath79_ddr_pci_win_base;
+
+void ath79_ddr_ctrl_init(void)
+{
+	ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
+					 AR71XX_DDR_CTRL_SIZE);
+	if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) {
+		ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
+		ath79_ddr_pci_win_base = 0;
+	} else {
+		ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
+		ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
+	}
+}
+EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
 
 void ath79_ddr_wb_flush(u32 reg)
 {
-	void __iomem *flush_reg = ath79_ddr_base + reg;
+	void __iomem *flush_reg = ath79_ddr_wb_flush_base + (4 * reg);
 
 	/* Flush the DDR write buffer. */
 	__raw_writel(0x1, flush_reg);
+#if defined(CONFIG_SOC_AR934X) || defined(CONFIG_SOC_QCA953X)
+	/* Save WMAC Glue Cause Reg in Sticky Reg if suspected hang */
+{
+	unsigned int cnt = 0;
+	unsigned int tmp = 0;
+
+	while (__raw_readl(flush_reg) & 0x1) {
+		if (cnt++ > 1024) {
+			tmp = __raw_readl(WMAC_GLUE_SYNC_CAUSE_REG);
+			__raw_writel(tmp, ATH79_RESET_STICKY_REG);
+		}
+	}
+}
+#else
 	while (__raw_readl(flush_reg) & 0x1)
 		;
+#endif
 
 	/* It must be run twice. */
 	__raw_writel(0x1, flush_reg);
@@ -56,6 +101,21 @@
 }
 EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush);
 
+void ath79_ddr_set_pci_windows(void)
+{
+	BUG_ON(!ath79_ddr_pci_win_base);
+
+	__raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0);
+	__raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 1);
+	__raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 2);
+	__raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 3);
+	__raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 4);
+	__raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 5);
+	__raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 6);
+	__raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 7);
+}
+EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows);
+
 void ath79_device_reset_set(u32 mask)
 {
 	unsigned long flags;
@@ -72,10 +132,16 @@
 		reg = AR933X_RESET_REG_RESET_MODULE;
 	else if (soc_is_ar934x())
 		reg = AR934X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca953x())
+		reg = QCA953X_RESET_REG_RESET_MODULE;
 	else if (soc_is_qca955x())
 		reg = QCA955X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca956x() || soc_is_tp9343())
+		reg = QCA956X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qcn550x())
+		reg = QCN550X_RESET_REG_RESET_MODULE;
 	else
-		BUG();
+		panic("Reset register not defined for this SOC");
 
 	spin_lock_irqsave(&ath79_device_reset_lock, flags);
 	t = ath79_reset_rr(reg);
@@ -100,10 +166,16 @@
 		reg = AR933X_RESET_REG_RESET_MODULE;
 	else if (soc_is_ar934x())
 		reg = AR934X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca953x())
+		reg = QCA953X_RESET_REG_RESET_MODULE;
 	else if (soc_is_qca955x())
 		reg = QCA955X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca956x() || soc_is_tp9343())
+		reg = QCA956X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qcn550x())
+		reg = QCN550X_RESET_REG_RESET_MODULE;
 	else
-		BUG();
+		panic("Reset register not defined for this SOC");
 
 	spin_lock_irqsave(&ath79_device_reset_lock, flags);
 	t = ath79_reset_rr(reg);
@@ -111,3 +183,46 @@
 	spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
 }
 EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
+
+u32 ath79_device_reset_get(u32 mask)
+{
+	unsigned long flags;
+	u32 reg;
+	u32 ret;
+
+	if (soc_is_ar71xx())
+		reg = AR71XX_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar724x())
+		reg = AR724X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar913x())
+		reg = AR913X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar933x())
+		reg = AR933X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar934x())
+		reg = AR934X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca956x() || soc_is_tp9343())
+		reg = QCA956X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qcn550x())
+		reg = QCN550X_RESET_REG_RESET_MODULE;
+	else
+		BUG();
+
+	spin_lock_irqsave(&ath79_device_reset_lock, flags);
+	ret = ath79_reset_rr(reg);
+	spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(ath79_device_reset_get);
+
+void ath79_flash_acquire(void)
+{
+	mutex_lock(&ath79_flash_mutex);
+}
+EXPORT_SYMBOL_GPL(ath79_flash_acquire);
+
+void ath79_flash_release(void)
+{
+	mutex_unlock(&ath79_flash_mutex);
+}
+EXPORT_SYMBOL_GPL(ath79_flash_release);
+