--- zzzz-none-000/linux-3.10.107/arch/mips/ath79/setup.c 2017-06-27 09:49:32.000000000 +0000 +++ scorpion-7490-727/linux-3.10.107/arch/mips/ath79/setup.c 2021-02-04 17:41:59.000000000 +0000 @@ -17,18 +17,36 @@ #include #include #include +#include +#include +#include #include #include #include /* for mips_hpt_frequency */ #include /* for _machine_{restart,halt} */ #include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include #include #include #include "common.h" #include "dev-common.h" #include "machtypes.h" +#include #define ATH79_SYS_TYPE_LEN 64 @@ -36,15 +54,57 @@ #define AR724X_BASE_FREQ 5000000 #define AR913X_BASE_FREQ 5000000 +/*--------------------------------------------------------------------------------*\ +\*--------------------------------------------------------------------------------*/ +extern void ath_savelog_to_ram(void); +extern void set_reboot_status_to_NMI(void); +extern void set_reboot_status_to_NMI_WA(void); +extern void set_reboot_status_to_BusError(void); +extern void set_reboot_status_to_SoftReboot(void); + +extern void qca955x_setup(void); +extern void ar934x_setup(void); +extern void ar724x_setup(void); + +/*------------------------------------------------------------------------------------------*\ +\*------------------------------------------------------------------------------------------*/ static char ath79_sys_type[ATH79_SYS_TYPE_LEN]; +extern char __owrt_dtb[]; -static void ath79_restart(char *command) -{ - ath79_device_reset_set(AR71XX_RESET_FULL_CHIP); - for (;;) +void ath79_restart(char *command) { + unsigned int val = (1<<0); + + if (command) { + if ( ! strncmp(command, "watchdog", sizeof("watchdog") - 1)) { + val = (1<<1); + set_reboot_status_to_NMI(); + ath_savelog_to_ram(); + } else if ( ! strncmp(command, "nmi_workaround", sizeof("nmi_workaround") - 1)) { + val = (1<<2); + set_reboot_status_to_NMI_WA(); + ath_savelog_to_ram(); + } else if ( ! strncmp(command, "bus_error", sizeof("bus_error") - 1)) { + set_reboot_status_to_BusError(); + ath_savelog_to_ram(); + } + } else { + set_reboot_status_to_SoftReboot(); + if(oops_in_progress) { + /*--- wir kommen aus panic() ---*/ + ath_savelog_to_ram(); + } + } +#if !defined(CONFIG_SOC_AR724X) + ath_reg_wr(ATH_RESET_BASE + ATH_RESET_REG_STICKY, val); /*--- save-Rebootstatus ---*/ +#endif/*--- #if !defined(CONFIG_SOC_AR724X) ---*/ + + ath79_device_reset_set(ATH_RESET_FULL_CHIP); + for (;;) { if (cpu_wait) cpu_wait(); + } } +EXPORT_SYMBOL(ath79_restart); static void ath79_halt(void) { @@ -59,6 +119,7 @@ u32 major; u32 minor; u32 rev = 0; + u32 ver = 1; id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); major = id & REV_ID_MAJOR_MASK; @@ -151,6 +212,17 @@ rev = id & AR934X_REV_ID_REVISION_MASK; break; + case REV_ID_MAJOR_QCA9533_V2: + ver = 2; + ath79_soc_rev = 2; + /* drop through */ + + case REV_ID_MAJOR_QCA9533: + ath79_soc = ATH79_SOC_QCA9533; + chip = "9533"; + rev = id & QCA953X_REV_ID_REVISION_MASK; + break; + case REV_ID_MAJOR_QCA9556: ath79_soc = ATH79_SOC_QCA9556; chip = "9556"; @@ -163,17 +235,41 @@ rev = id & QCA955X_REV_ID_REVISION_MASK; break; + case REV_ID_MAJOR_QCA956X: + ath79_soc = ATH79_SOC_QCA956X; + chip = "956X"; + rev = id & QCA956X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_TP9343: + ath79_soc = ATH79_SOC_TP9343; + chip = "9343"; + rev = id & QCA956X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCN5502: + ath79_soc = ATH79_SOC_QCN5502; + chip = "5502"; + rev = id & QCN550X_REV_ID_REVISION_MASK; + break; + default: panic("ath79: unknown SoC, id:0x%08x", id); } - ath79_soc_rev = rev; + if (ver == 1) + ath79_soc_rev = rev; - if (soc_is_qca955x()) - sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", - chip, rev); + if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x() || + soc_is_qcn550x()) + snprintf(ath79_sys_type, sizeof(ath79_sys_type), + "Qualcomm Atheros QCA%s ver %u rev %u", chip, ver, rev); + else if (soc_is_tp9343()) + snprintf(ath79_sys_type, sizeof(ath79_sys_type), + "Qualcomm Atheros TP%s rev %u", chip, rev); else - sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); + snprintf(ath79_sys_type, sizeof(ath79_sys_type), + "Atheros AR%s rev %u", chip, rev); pr_info("SoC: %s\n", ath79_sys_type); } @@ -182,45 +278,220 @@ return ath79_sys_type; } -unsigned int __cpuinit get_c0_compare_int(void) +int get_c0_perfcount_int(void) +{ + return ATH79_MISC_IRQ(5); +} +EXPORT_SYMBOL_GPL(get_c0_perfcount_int); + +unsigned int get_c0_compare_int(void) { return CP0_LEGACY_COMPARE_IRQ; } -void __init plat_mem_setup(void) +/*------------------------------------------------------------------------------------------*\ +\*------------------------------------------------------------------------------------------*/ +int ath79_be_handler(struct pt_regs *regs, int is_fixup) { - set_io_port_base(KSEG1); + printk("ath data bus error: cause %#x\n", read_c0_cause()); - ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, - AR71XX_RESET_SIZE); - ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, - AR71XX_PLL_SIZE); - ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, - AR71XX_DDR_CTRL_SIZE); + return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL); +} - ath79_detect_sys_type(); - detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX); - ath79_clocks_init(); +/*------------------------------------------------------------------------------------------*\ +\*------------------------------------------------------------------------------------------*/ +void __init plat_device_tree_setup(void) { +#if defined CONFIG_AVM_ENHANCED + struct boot_param_header *dtb; + + char *rev_str; + int rev = 0; + char *subrev_str; + int subrev = 0; + + rev_str = prom_getenv("HWRevision"); + if (rev_str) { + if (sscanf(rev_str, "%u", &rev) != 1) { + rev_str = NULL; + } else { + switch (rev) { + case 190: + mips_machtype = ATH79_MACH_AVM_HW190; + break; + case 194: + mips_machtype = ATH79_MACH_AVM_HW194; + break; + case 200: + mips_machtype = ATH79_MACH_AVM_HW200; + break; + case 201: + mips_machtype = ATH79_MACH_AVM_HW201; + break; + case 205: + mips_machtype = ATH79_MACH_AVM_HW205; + break; + case 206: + mips_machtype = ATH79_MACH_AVM_HW206; + break; + case 214: + mips_machtype = ATH79_MACH_AVM_HW214; + break; + case 215: + mips_machtype = ATH79_MACH_AVM_HW215; + break; + case 216: + mips_machtype = ATH79_MACH_AVM_HW216; + break; + case 219: + mips_machtype = ATH79_MACH_AVM_HW219; + break; + case 222: + mips_machtype = ATH79_MACH_AVM_HW222; + break; + case 238: + mips_machtype = ATH79_MACH_AVM_HW238; + break; + case 240: + mips_machtype = ATH79_MACH_AVM_HW240; + break; + case 241: + mips_machtype = ATH79_MACH_AVM_HW241; + break; + case 254: + mips_machtype = ATH79_MACH_AVM_HW254; + break; + case 263: + mips_machtype = ATH79_MACH_AVM_HW263; + break; + default: + pr_err("%s: Unknown HWRevision %d for ATH79 Architecture\n", __func__, rev); + rev_str = NULL; + break; + } + } + } + if (!rev_str) { + printk("%s: Unable to read AVM hardware " + "Revision! Identity crisis... who am I?\n", + __func__); + } + + subrev_str = prom_getenv("HWSubRevision"); + if (subrev_str) { + if (sscanf(subrev_str, "%u", &subrev) != 1) + subrev_str = NULL; + } + if (!subrev_str) { + printk("%s: Unable to read AVM hardware " + "subrevision! Identity crisis... who am I?\n", + __func__); + } + + dtb = avm_fw_embedded_dtb(); + + if (!dtb) { + printk("%s: Missing device-tree for AVM hardware " + "subrevision %d\n", __func__, subrev); + panic("%s: Missing device-tree for AVM hardware " + "subrevision %d\n", __func__, subrev); + } else { + extern void *initial_boot_params; + initial_boot_params = (void *) dtb; + printk("DT @ %p: %02x %02x %02x %02x %02x %02x %02x %02x\n", + dtb, + ((unsigned char *)dtb)[0], + ((unsigned char *)dtb)[1], + ((unsigned char *)dtb)[2], + ((unsigned char *)dtb)[3], + ((unsigned char *)dtb)[4], + ((unsigned char *)dtb)[5], + ((unsigned char *)dtb)[6], + ((unsigned char *)dtb)[7]); + } + __dt_setup_arch(dtb); + +#endif +} +void __init plat_mem_setup(void) +{ + char *s, *p; + unsigned int memsize = 0; + phys_addr_t memstart = PHYS_OFFSET; + + board_be_handler = ath79_be_handler; _machine_restart = ath79_restart; _machine_halt = ath79_halt; pm_power_off = ath79_halt; + printk("Set Port base\n"); + set_io_port_base(KSEG1); + printk("detect_sys_type\n"); + + + ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, AR71XX_RESET_SIZE); + ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE , AR71XX_PLL_SIZE ); + + ath79_detect_sys_type(); + + s = prom_getenv("memsize"); + if (s) { + memsize = simple_strtoul(s, &p, 16); + } else { + printk("[%s] memsize konnte nicht aus env ermittelt werden\n", __func__); + BUG_ON(1); + } + + /* Use when SQFS is positioned directly behind the kernel-image */ + s = prom_getenv("memstart"); + if (s) { + printk("[%s] found memstart in env\n", __func__); + memstart = simple_strtoul(s, &p, 16); + } + + printk("[%s] memsize 0x%x, memstart 0x%08x\n", __func__, memsize, memstart); + + add_memory_region(memstart, memsize, BOOT_MEM_RAM); } void __init plat_time_init(void) { - struct clk *clk; + unsigned long cpu_clk_rate; + unsigned long ahb_clk_rate; + unsigned long ddr_clk_rate; + unsigned long ref_clk_rate; + + ath79_clocks_init(); - clk = clk_get(NULL, "cpu"); - if (IS_ERR(clk)) - panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + cpu_clk_rate = ath79_get_sys_clk_rate("cpu"); + ahb_clk_rate = ath79_get_sys_clk_rate("ahb"); + ddr_clk_rate = ath79_get_sys_clk_rate("ddr"); + ref_clk_rate = ath79_get_sys_clk_rate("ref"); + + pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n", + cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000, + ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000, + ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000, + ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000); - mips_hpt_frequency = clk_get_rate(clk) / 2; + mips_hpt_frequency = cpu_clk_rate / 2; } +__setup("board=", mips_machtype_setup); + static int __init ath79_setup(void) { - ath79_gpio_init(); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + if (mips_machtype == ATH79_MACH_GENERIC_OF) { +#if defined(ATH79_WLAN_FW_DUMP) + ath79_init_wlan_fw_dump_buffer(); +#endif + return 0; + } + +/* === Replaced by AVM Implementatio === */ +#if 0 + ath79_gpio_init(); +#endif ath79_register_uart(); ath79_register_wdt(); @@ -231,6 +502,22 @@ arch_initcall(ath79_setup); +void __init device_tree_init(void) +{ + unsigned long base, size; + + if (!initial_boot_params) + return; + + base = virt_to_phys(initial_boot_params); + size = be32_to_cpu(of_get_flat_dt_size()); + + /* Before we do anything, lets reserve the dt blob */ + reserve_bootmem(base, size, BOOTMEM_DEFAULT); + + unflatten_device_tree(); +} + static void __init ath79_generic_init(void) { /* Nothing to do */ @@ -240,3 +527,8 @@ "Generic", "Generic AR71XX/AR724X/AR913X based board", ath79_generic_init); + +MIPS_MACHINE(ATH79_MACH_GENERIC_OF, + "DTB", + "Generic AR71XX/AR724X/AR913X based board (DT)", + NULL);