--- zzzz-none-000/linux-3.10.107/arch/mips/kernel/genex.S 2017-06-27 09:49:32.000000000 +0000 +++ scorpion-7490-727/linux-3.10.107/arch/mips/kernel/genex.S 2021-02-04 17:41:59.000000000 +0000 @@ -21,20 +21,6 @@ #include #include -#ifdef CONFIG_MIPS_MT_SMTC -#define PANIC_PIC(msg) \ - .set push; \ - .set nomicromips; \ - .set reorder; \ - PTR_LA a0,8f; \ - .set noat; \ - PTR_LA AT, panic; \ - jr AT; \ -9: b 9b; \ - .set pop; \ - TEXT(msg) -#endif - __INIT /* @@ -67,7 +53,7 @@ */ NESTED(except_vec3_r4000, 0, sp) .set push - .set mips3 + .set mips64r2 .set noat mfc0 k1, CP0_CAUSE li k0, 31<<2 @@ -139,7 +125,7 @@ nop nop #endif - .set mips3 + .set MIPS_ISA_ARCH_LEVEL_RAW wait /* end of rollback region (the region size must be power of two) */ 1: @@ -205,6 +191,9 @@ PTR_LA ra, ret_from_irq PTR_LA v0, plat_irq_dispatch jr v0 +#if defined(CONFIG_AVM_SIMPLE_PROFILING) + move a0, sp +#endif /*--- #if defined(CONFIG_AVM_SIMPLE_PROFILING) ---*/ #ifdef CONFIG_CPU_MICROMIPS nop #endif @@ -251,16 +240,10 @@ SAVE_AT .set push .set noreorder -#ifdef CONFIG_MIPS_MT_SMTC - /* - * To keep from blindly blocking *all* interrupts - * during service by SMTC kernel, we also want to - * pass the IM value to be cleared. - */ -FEXPORT(except_vec_vi_mori) - ori a0, $0, 0 -#endif /* CONFIG_MIPS_MT_SMTC */ PTR_LA v1, except_vec_vi_handler +#if defined(CONFIG_AVM_SIMPLE_PROFILING) + move a0, sp +#endif /*--- #if defined(CONFIG_AVM_SIMPLE_PROFILING) ---*/ FEXPORT(except_vec_vi_lui) lui v0, 0 /* Patched */ jr v1 @@ -277,43 +260,19 @@ NESTED(except_vec_vi_handler, 0, sp) SAVE_TEMP SAVE_STATIC -#ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC has an interesting problem that interrupts are level-triggered, - * and the CLI macro will clear EXL, potentially causing a duplicate - * interrupt service invocation. So we need to clear the associated - * IM bit of Status prior to doing CLI, and restore it after the - * service routine has been invoked - we must assume that the - * service routine will have cleared the state, and any active - * level represents a new or otherwised unserviced event... - */ - mfc0 t1, CP0_STATUS - and t0, a0, t1 -#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP - mfc0 t2, CP0_TCCONTEXT - or t2, t0, t2 - mtc0 t2, CP0_TCCONTEXT -#endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */ - xor t1, t1, t0 - mtc0 t1, CP0_STATUS - _ehb -#endif /* CONFIG_MIPS_MT_SMTC */ CLI #ifdef CONFIG_TRACE_IRQFLAGS move s0, v0 -#ifdef CONFIG_MIPS_MT_SMTC - move s1, a0 -#endif TRACE_IRQS_OFF -#ifdef CONFIG_MIPS_MT_SMTC - move a0, s1 -#endif move v0, s0 #endif LONG_L s0, TI_REGS($28) LONG_S sp, TI_REGS($28) PTR_LA ra, ret_from_irq +#if defined(CONFIG_AVM_SIMPLE_PROFILING) + move a0, sp /*--- AVM IRQ ---*/ +#endif /*--- #if defined(CONFIG_AVM_SIMPLE_PROFILING) ---*/ jr v0 END(except_vec_vi_handler) @@ -340,7 +299,7 @@ ejtag_return: MFC0 k0, CP0_DESAVE - .set mips32 + .set mips64r2 deret .set pop END(ejtag_debug_handler) @@ -363,23 +322,49 @@ * unconditional jump to this vector. */ NESTED(except_vec_nmi, 0, sp) +#ifdef CONFIG_QCA_NMI_RESERVE + /* + * The following code will be linked in the kseg0 (0x8xxx_xxxx) range. + * However, it will get executed from kseg2 (0xCxxx_xxxx) range. Hence, + * this has to be position independent. + */ + MTC0 k0, CP0_DESAVE /* Save k0 for nmi_handler */ + la k0, nmi_handler + j k0 + nop +#else j nmi_handler #ifdef CONFIG_CPU_MICROMIPS nop #endif +#endif END(except_vec_nmi) +#ifdef CONFIG_QCA_NMI_RESERVE +EXPORT(except_vec_nmi_end) +#endif __FINIT NESTED(nmi_handler, PT_SIZE, sp) .set push .set noat + /* + * Clear ERL - restore segment mapping + * Clear BEV - required for page fault exception handler to work + */ + mfc0 k0, CP0_STATUS + ori k0, k0, ST0_EXL + li k1, ~(ST0_BEV | ST0_ERL) + and k0, k0, k1 + mtc0 k0, CP0_STATUS + _ehb +#ifdef CONFIG_QCA_NMI_RESERVE + MFC0 k0, CP0_DESAVE /* Restore k0 saved by except_vec_nmi */ +#endif SAVE_ALL move a0, sp jal nmi_exception_handler - RESTORE_ALL - .set mips3 - eret + /* nmi_exception_handler never returns */ .set pop END(nmi_handler) @@ -399,14 +384,18 @@ .macro __build_clear_fpe .set push /* gas fails to assemble cfc1 for some archs (octeon).*/ \ - .set mips1 + .set mips64r2 + SET_HARDFLOAT cfc1 a1, fcr31 - li a2, ~(0x3f << 12) - and a2, a1 - ctc1 a2, fcr31 .set pop - TRACE_IRQS_ON - STI + CLI + TRACE_IRQS_OFF + .endm + + .macro __build_clear_msa_fpe + _cfcmsa a1, MSA_CSR + CLI + TRACE_IRQS_OFF .endm .macro __build_clear_ade @@ -445,7 +434,7 @@ .set noat SAVE_ALL FEXPORT(handle_\exception\ext) - __BUILD_clear_\clear + __build_clear_\clear .set at __BUILD_\verbose \exception move a0, sp @@ -467,7 +456,10 @@ BUILD_HANDLER cpu cpu sti silent /* #11 */ BUILD_HANDLER ov ov sti silent /* #12 */ BUILD_HANDLER tr tr sti silent /* #13 */ + BUILD_HANDLER msa_fpe msa_fpe msa_fpe silent /* #14 */ BUILD_HANDLER fpe fpe fpe silent /* #15 */ + BUILD_HANDLER ftlb ftlb none silent /* #16 */ + BUILD_HANDLER msa msa sti silent /* #21 */ BUILD_HANDLER mdmx mdmx sti silent /* #22 */ #ifdef CONFIG_HARDWARE_WATCHPOINTS /* @@ -485,9 +477,6 @@ .align 5 LEAF(handle_ri_rdhwr_vivt) -#ifdef CONFIG_MIPS_MT_SMTC - PANIC_PIC("handle_ri_rdhwr_vivt called") -#else .set push .set noat .set noreorder @@ -506,7 +495,6 @@ .set pop bltz k1, handle_ri /* slow path */ /* fall thru */ -#endif END(handle_ri_rdhwr_vivt) LEAF(handle_ri_rdhwr) @@ -566,7 +554,7 @@ ori k1, _THREAD_MASK xori k1, _THREAD_MASK LONG_L v1, TI_TP_VALUE(k1) - .set mips3 + .set mips64r2 eret .set mips0 #endif