--- zzzz-none-000/linux-3.10.107/drivers/mtd/devices/m25p80.c 2017-06-27 09:49:32.000000000 +0000 +++ scorpion-7490-727/linux-3.10.107/drivers/mtd/devices/m25p80.c 2021-02-04 17:41:59.000000000 +0000 @@ -15,886 +15,549 @@ * */ -#include #include #include #include #include -#include -#include -#include -#include -#include -#include -#include #include #include -#include #include #include +#include -/* Flash opcodes. */ -#define OPCODE_WREN 0x06 /* Write enable */ -#define OPCODE_RDSR 0x05 /* Read status register */ -#define OPCODE_WRSR 0x01 /* Write status register 1 byte */ -#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ -#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ -#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ -#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ -#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ -#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ -#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ -#define OPCODE_RDID 0x9f /* Read JEDEC ID */ - -/* Used for SST flashes only. */ -#define OPCODE_BP 0x02 /* Byte program */ -#define OPCODE_WRDI 0x04 /* Write disable */ -#define OPCODE_AAI_WP 0xad /* Auto address increment word program */ - -/* Used for Macronix flashes only. */ -#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */ -#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */ - -/* Used for Spansion flashes only. */ -#define OPCODE_BRWR 0x17 /* Bank register write */ - -/* Status Register bits. */ -#define SR_WIP 1 /* Write in progress */ -#define SR_WEL 2 /* Write enable latch */ -/* meaning of other SR_* bits may differ between vendors */ -#define SR_BP0 4 /* Block protect 0 */ -#define SR_BP1 8 /* Block protect 1 */ -#define SR_BP2 0x10 /* Block protect 2 */ -#define SR_SRWD 0x80 /* SR write protect */ - -/* Define max times to check status register before we give up. */ -#define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */ -#define MAX_CMD_SIZE 5 - -#define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16) - -/****************************************************************************/ - +#define MAX_CMD_SIZE 6 struct m25p { struct spi_device *spi; - struct mutex lock; - struct mtd_info mtd; - u16 page_size; - u16 addr_width; - u8 erase_opcode; - u8 *command; - bool fast_read; + struct spi_nor spi_nor; + u8 command[MAX_CMD_SIZE]; }; -static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd) -{ - return container_of(mtd, struct m25p, mtd); -} - -/****************************************************************************/ - -/* - * Internal helper functions - */ - -/* - * Read the status register, returning its value in the location - * Return the status register value. - * Returns negative if error occurred. - */ -static int read_sr(struct m25p *flash) -{ - ssize_t retval; - u8 code = OPCODE_RDSR; - u8 val; - - retval = spi_write_then_read(flash->spi, &code, 1, &val, 1); - - if (retval < 0) { - dev_err(&flash->spi->dev, "error %d reading SR\n", - (int) retval); - return retval; - } +#if defined(CONFIG_TFFS_DEV_LEGACY) - return val; -} +#include +#include +#include +#include +#include +#include "../../spi/spi_qup.h" +#include -/* - * Write status register 1 byte - * Returns negative if error occurred. - */ -static int write_sr(struct m25p *flash, u8 val) -{ - flash->command[0] = OPCODE_WRSR; - flash->command[1] = val; +#define OPCODE_RDSR 0x05 /* Read status register */ +#define OPCODE_RDID 0x9f /* Read JEDEC ID */ +#define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */ - return spi_write(flash->spi, flash->command, 2); -} +bool use_spi_sync = false; -/* - * Set write enable latch with Write Enable command. - * Returns negative if error occurred. - */ -static inline int write_enable(struct m25p *flash) +static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd) { - u8 code = OPCODE_WREN; - - return spi_write_then_read(flash->spi, &code, 1, NULL, 0); + return container_of(mtd, struct m25p, spi_nor.mtd); } /* - * Send write disble instruction to the chip. + * Functions for directly accessing SPI */ -static inline int write_disable(struct m25p *flash) +static inline bool spi_qup_is_valid_state(struct spi_qup *dd) { - u8 code = OPCODE_WRDI; + u32 spi_op = readl(dd->base + SPI_STATE); - return spi_write_then_read(flash->spi, &code, 1, NULL, 0); + return spi_op & SPI_OP_STATE_VALID; } -/* - * Enable/disable 4-byte addressing mode. - */ -static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable) +static inline int spi_qup_wait_valid(struct spi_qup *dd) { - switch (JEDEC_MFR(jedec_id)) { - case CFI_MFR_MACRONIX: - case 0xEF /* winbond */: - flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B; - return spi_write(flash->spi, flash->command, 1); - default: - /* Spansion style */ - flash->command[0] = OPCODE_BRWR; - flash->command[1] = enable << 7; - return spi_write(flash->spi, flash->command, 2); - } -} + unsigned long delay; -/* - * Service routine to read status register until ready, or timeout occurs. - * Returns non-zero if error. - */ -static int wait_till_ready(struct m25p *flash) -{ - unsigned long deadline; - int sr; + /* + * For small delay values, the default timeout would + * be one jiffy + */ + delay = SPI_DELAY_THRESHOLD; + /* Use some random high number here that just works. */ + if (delay < 16) { + delay = 166; + } - deadline = jiffies + MAX_READY_WAIT_JIFFIES; + while (!spi_qup_is_valid_state(dd) && --delay) { + mdelay(1); + } - do { - if ((sr = read_sr(flash)) < 0) - break; - else if (!(sr & SR_WIP)) - return 0; + if (!spi_qup_is_valid_state(dd)) { + dev_err(dd->dev, "%s: SPI operational state" + " not valid\n", __func__); + return -ETIMEDOUT; + } - cond_resched(); + return 0; +} - } while (!time_after_eq(jiffies, deadline)); +static inline int spi_qup_get_state(struct spi_qup *dd) { + if (spi_qup_wait_valid(dd)) { + pr_err("[%s] spi_qup_wait_valid failed\n", __func__); + return -EIO; + } - return 1; + return (readl(dd->base + SPI_STATE) & SPI_OP_STATE); } -/* - * Erase the whole flash memory - * - * Returns 0 if successful, non-zero otherwise. - */ -static int erase_chip(struct m25p *flash) +static inline int spi_qup_set_state(struct spi_qup *dd, + enum spi_qup_state state) { - pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__, - (long long)(flash->mtd.size >> 10)); + enum spi_qup_state cur_state; + int tmp; - /* Wait until finished previous write command. */ - if (wait_till_ready(flash)) - return 1; + if (spi_qup_wait_valid(dd)) { + return -EIO; + } - /* Send write enable, then erase commands. */ - write_enable(flash); + tmp = readl(dd->base + SPI_STATE); + cur_state = tmp & SPI_OP_STATE; - /* Set up command buffer. */ - flash->command[0] = OPCODE_CHIP_ERASE; + /* Per spec: + For PAUSE_STATE to RESET_STATE, two writes of (10) are required */ + if ((cur_state == SPI_OP_STATE_PAUSE) && (state == SPI_OP_STATE_RESET)) { + writel(SPI_OP_STATE_CLEAR_BITS, dd->base + SPI_STATE); + writel(SPI_OP_STATE_CLEAR_BITS, dd->base + SPI_STATE); + } else { + writel((tmp & ~SPI_OP_STATE) | state, + dd->base + SPI_STATE); + } - spi_write(flash->spi, flash->command, 1); + if (spi_qup_wait_valid(dd)) { + return -EIO; + } return 0; } -static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd) -{ - /* opcode is in cmd[0] */ - cmd[1] = addr >> (flash->addr_width * 8 - 8); - cmd[2] = addr >> (flash->addr_width * 8 - 16); - cmd[3] = addr >> (flash->addr_width * 8 - 24); - cmd[4] = addr >> (flash->addr_width * 8 - 32); -} - -static int m25p_cmdsz(struct m25p *flash) -{ - return 1 + flash->addr_width; -} - -/* - * Erase one sector of flash memory at offset ``offset'' which is any - * address within the sector which should be erased. - * - * Returns 0 if successful, non-zero otherwise. - */ -static int erase_sector(struct m25p *flash, u32 offset) -{ - pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev), - __func__, flash->mtd.erasesize / 1024, offset); +static inline int spi_qup_stop(struct spi_device *spi) { + struct spi_qup *dd = spi_master_get_devdata(spi->master); + int retval; + // Wait until done sending (should be done here anyways...) + retval = readl(dd->base + SPI_OPERATIONAL); + while (retval & SPI_OP_OP_FIFO_NOT_EMPTY) { + retval = readl(dd->base + SPI_OPERATIONAL); + } - /* Wait until finished previous write command. */ - if (wait_till_ready(flash)) - return 1; + // Force CS inactive + retval = readl(dd->base + SPI_IO_CONTROL); + writel(retval & ~SPI_IO_C_FORCE_CS, dd->base + SPI_IO_CONTROL); + if (gpio_is_valid(spi->cs_gpio)) { + gpio_set_value(spi->cs_gpio, true); + } - /* Send write enable, then erase commands. */ - write_enable(flash); + retval = spi_qup_set_state(dd, SPI_OP_STATE_RESET); + if (retval) { + dev_err(dd->dev, + "[%s] Error setting QUP to reset-state\n", + __func__); + } - /* Set up command buffer. */ - flash->command[0] = flash->erase_opcode; - m25p_addr2cmd(flash, offset, flash->command); + return retval; +} - spi_write(flash->spi, flash->command, m25p_cmdsz(flash)); +static inline int spi_qup_start(struct spi_device *spi) { + struct spi_qup *dd = spi_master_get_devdata(spi->master); + int retval; + int tmp; - return 0; -} + spi_qup_stop(spi); -/****************************************************************************/ + retval = spi_qup_prepare_for_write(dd); + if (retval) { + dev_err(dd->dev, "[%s] Prepare_for_write failed\n", __func__); + } -/* - * MTD implementation - */ + // Force CS active + tmp = readl(dd->base + SPI_IO_CONTROL); + writel(tmp | SPI_IO_C_FORCE_CS, dd->base + SPI_IO_CONTROL); -/* - * Erase an address range on the flash chip. The address range may extend - * one or more erase sectors. Return an error is there is a problem erasing. - */ -static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr) -{ - struct m25p *flash = mtd_to_m25p(mtd); - u32 addr,len; - uint32_t rem; - - pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev), - __func__, (long long)instr->addr, - (long long)instr->len); - - div_u64_rem(instr->len, mtd->erasesize, &rem); - if (rem) - return -EINVAL; - - addr = instr->addr; - len = instr->len; - - mutex_lock(&flash->lock); - - /* whole-chip erase? */ - if (len == flash->mtd.size) { - if (erase_chip(flash)) { - instr->state = MTD_ERASE_FAILED; - mutex_unlock(&flash->lock); - return -EIO; - } - - /* REVISIT in some cases we could speed up erasing large regions - * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up - * to use "small sector erase", but that's not always optimal. - */ + if (gpio_is_valid(spi->cs_gpio)) { + gpio_set_value(spi->cs_gpio, false); + } - /* "sector"-at-a-time erase */ - } else { - while (len) { - if (erase_sector(flash, addr)) { - instr->state = MTD_ERASE_FAILED; - mutex_unlock(&flash->lock); - return -EIO; - } - - addr += mtd->erasesize; - len -= mtd->erasesize; - } - } + return retval; +} - mutex_unlock(&flash->lock); +static int spi_rw_sync(struct spi_device *spi, const void *txbuf, + void *rxbuf, unsigned buf_size) { + struct spi_qup *dd = spi_master_get_devdata(spi->master); - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); + if (!buf_size) { + return 0; + } - return 0; -} + dd->tx_buf = txbuf; + dd->tx_bytes = buf_size; + dd->rx_buf = rxbuf; + dd->rx_bytes = buf_size; -/* - * Read an address range from the flash chip. The address range - * may be any size provided it is within the physical boundaries. - */ -static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, u_char *buf) -{ - struct m25p *flash = mtd_to_m25p(mtd); - struct spi_transfer t[2]; - struct spi_message m; - uint8_t opcode; + if (spi_qup_get_state(dd) != SPI_OP_STATE_RUN) { + spi_qup_start(spi); + } - pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev), - __func__, (u32)from, len); + writel(dd->tx_buf?((unsigned int)*(dd->tx_buf++) << 0x18):0, dd->base + SPI_OUTPUT_FIFO); + dd->tx_bytes--; - spi_message_init(&m); - memset(t, 0, (sizeof t)); + spi_qup_set_state(dd, SPI_OP_STATE_RUN); + while (dd->rx_bytes) { + uint32_t op = readl(dd->base + SPI_OPERATIONAL); - /* NOTE: - * OPCODE_FAST_READ (if available) is faster. - * Should add 1 byte DUMMY_BYTE. - */ - t[0].tx_buf = flash->command; - t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0); - spi_message_add_tail(&t[0], &m); + if ((!(op & SPI_OP_OUTPUT_FIFO_FULL)) && dd->tx_bytes) { + writel(dd->tx_buf?((unsigned int)*(dd->tx_buf++) << 0x18):0, dd->base + SPI_OUTPUT_FIFO); + dd->tx_bytes--; + } - t[1].rx_buf = buf; - t[1].len = len; - spi_message_add_tail(&t[1], &m); + if (op & SPI_OP_IP_FIFO_NOT_EMPTY) { + volatile u32 tmp_r = readl(dd->base + SPI_INPUT_FIFO); + if (dd->rx_buf) *(dd->rx_buf++) = tmp_r; + dd->rx_bytes--; + } + } - mutex_lock(&flash->lock); + return 0; +} - /* Wait till previous write/erase is done. */ - if (wait_till_ready(flash)) { - /* REVISIT status return?? */ - mutex_unlock(&flash->lock); - return 1; - } +static int spi_write_then_read_sync(struct spi_device *spi, + const void *txbuf, unsigned n_tx, void *rxbuf, + unsigned n_rx) { + int retval; - /* FIXME switch to OPCODE_FAST_READ. It's required for higher - * clocks; and at this writing, every chip this driver handles - * supports that opcode. - */ + retval = spi_rw_sync(spi, txbuf, NULL, n_tx); + if (retval) return retval; + return spi_rw_sync(spi, NULL, rxbuf, n_rx); +} - /* Set up the write data buffer. */ - opcode = flash->fast_read ? OPCODE_FAST_READ : OPCODE_NORM_READ; - flash->command[0] = opcode; - m25p_addr2cmd(flash, from, flash->command); +static int spi_write_sync(struct spi_device *spi, + const void *buf, size_t len) { + return spi_rw_sync(spi, buf, NULL, len); +} - spi_sync(flash->spi, &m); +static int wait_till_ready(struct m25p *flash); +/*--- TFFS stuff ---*/ - *retlen = m.actual_length - m25p_cmdsz(flash) - - (flash->fast_read ? 1 : 0); +static DEFINE_SPINLOCK(panic_locking); - mutex_unlock(&flash->lock); +static inline void panic_lock(unsigned long *flags) +{ + spin_lock_irqsave(&panic_locking, *flags); +} - return 0; +static inline void panic_unlock(unsigned long flags) +{ + spin_unlock_irqrestore(&panic_locking, flags); } -/* - * Write an address range to the flash chip. Data must be written in - * FLASH_PAGESIZE chunks. The address range may be any size provided - * it is within the physical boundaries. - */ -static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const u_char *buf) +static int read_sr(struct m25p *flash) { - struct m25p *flash = mtd_to_m25p(mtd); - u32 page_offset, page_size; - struct spi_transfer t[2]; - struct spi_message m; + ssize_t retval; + u8 code = OPCODE_RDSR; + u8 val; + + retval = spi_write_then_read_sync(flash->spi, + &code, 1, &val, 1); + spi_qup_stop(flash->spi); - pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev), - __func__, (u32)to, len); + return val; +} - spi_message_init(&m); - memset(t, 0, (sizeof t)); +static int wait_till_ready(struct m25p *flash) +{ + unsigned long deadline; + int sr; + unsigned long delay_cnt = MAX_READY_WAIT_JIFFIES << 2; + + deadline = jiffies + MAX_READY_WAIT_JIFFIES; + // Just wait some time... + do { + if ((sr = read_sr(flash)) < 0) + break; + else if (!(sr & SR_WIP)) + return 0; + } while(--delay_cnt); + pr_err("SPI: Flash not ready!\n"); + return 1; +} + +static inline struct mtd_info *panic_reinit(struct mtd_info *mtd) { + unsigned long flags; + struct m25p *flash = mtd_to_m25p(mtd); + struct spi_device *spi = flash->spi; + struct spi_qup *dd = spi_master_get_devdata(spi->master); + int retval; + u8 code = OPCODE_RDID; + u8 id[3]; + + pm_runtime_irq_safe(dd->dev); + pm_runtime_get_sync(dd->dev); + clk_set_rate(dd->cclk, spi->max_speed_hz); + +// TODO: Expand this driver to remember incomplete write operations and complete them here to increase data consistency. + pr_err("[%s] called for mtd %s\n", __func__, mtd->name); + panic_lock(&flags); + // Disable IRQs + writel(QUP_OP_MASK_OUTPUT_SERVICE_FLAG | QUP_OP_MASK_INPUT_SERVICE_FLAG, + dd->base + QUP_OPERATIONAL_MASK); + disable_irq(dd->irq); + use_spi_sync = 1; + // Reset QUP core + writel(1, dd->base + SPI_SW_RESET); + // Wait for valid state + spi_qup_wait_valid(dd); + // Disable IRQs + writel(QUP_OP_MASK_OUTPUT_SERVICE_FLAG | QUP_OP_MASK_INPUT_SERVICE_FLAG, + dd->base + QUP_OPERATIONAL_MASK); + // Setup SPI mini core: + // N=7 (8 bit); SPI core; + writel(7 | (1 << 8), dd->base + QUP_CONFIG); + // Setup I/O modes register: FIFO for input and output (0) - a5 schreibt eigentlich in RO-Bereich... + writel(0, dd->base + SPI_IO_MODES); + // Disable error flags. Don't need them when working synchronously. + writel(0, dd->base + SPI_ERROR_FLAGS_EN); + // Leave all MX_COUNT registers in reset state (0) + // SPI configuration: Master, not HighSpeed ... + writel((spi->mode & SPI_CPHA)?0:SPI_CFG_INPUT_FIRST, dd->base + SPI_CONFIG); + // SPI I/O control: set CPOL, select cs line, (force chip select) + // set CS polarity (active LOW = 0), clock polarity... + writel(SPI_IO_C_NO_TRI_STATE | ((spi->mode & SPI_CPOL)?SPI_IO_C_CLK_IDLE_HIGH:0) | + (spi->chip_select << 2) | /* SPI_IO_C_FORCE_CS | */ SPI_IO_C_MX_CS_MODE + , dd->base + SPI_IO_CONTROL); + writel(0, dd->base + QUP_ERROR_FLAGS_EN); + + retval = wait_till_ready(flash); + if (retval) { + pr_err("[%s] Failed to read flash status (2) -- giving up.\n", __func__); + return NULL; + } + + // read ID + if (spi_write_then_read_sync(spi, &code, 1, id, 3)) { + spi_qup_stop(spi); + pr_err("[%s] Failed to read flash jedec ID\n", __func__); + panic_unlock(flags); + return NULL; + } + spi_qup_stop(spi); + retval = 0; + retval |= id[0]; + retval <<= 8; + retval |= id[1]; + retval <<= 8; + retval |= id[2]; + pr_err("%x\n", retval); +#if 0 + pr_err("%x >< %x\n", re) + if (info->jedec_id != retval) + pr_warn("[%s] Flash jedec ID mismatch (read: 0x%08x, expected: 0x%08x)\n", + __func__, retval, info->jedec_id); +#endif + panic_unlock(flags); + pr_info("[%s] ok; sync_spi = %x\n", __func__, use_spi_sync); + return mtd; - t[0].tx_buf = flash->command; - t[0].len = m25p_cmdsz(flash); - spi_message_add_tail(&t[0], &m); +} - t[1].tx_buf = buf; - spi_message_add_tail(&t[1], &m); +static int avm_spi_write_then_read(struct spi_device *spi, const void *txbuf, unsigned n_tx, void *rxbuf, unsigned n_rx) +{ + int ret; - mutex_lock(&flash->lock); + if (unlikely(use_spi_sync)) { + ret = spi_write_then_read_sync(spi, txbuf, n_tx, rxbuf, n_rx); + spi_qup_stop(spi); + } + else { + ret = spi_write_then_read(spi, txbuf, n_tx, rxbuf, n_rx); + } - /* Wait until finished previous write command. */ - if (wait_till_ready(flash)) { - mutex_unlock(&flash->lock); - return 1; - } + return ret; +} - write_enable(flash); +static int avm_spi_write(struct spi_device *spi, const void *txbuf, unsigned n_tx) { + int ret; - /* Set up the opcode in the write buffer. */ - flash->command[0] = OPCODE_PP; - m25p_addr2cmd(flash, to, flash->command); + if (unlikely(use_spi_sync)) { + ret = spi_write_sync(spi, txbuf, n_tx); + spi_qup_stop(spi); + } + else { + ret = spi_write(spi, txbuf, n_tx); + } - page_offset = to & (flash->page_size - 1); + return ret; +} - /* do all the bytes fit onto one page? */ - if (page_offset + len <= flash->page_size) { - t[1].len = len; +static int avm_spi_sync(struct spi_device *spi, struct spi_message *msg) { + int ret; + struct spi_transfer *t; + unsigned len = 0; - spi_sync(flash->spi, &m); + if (unlikely(use_spi_sync)) { + list_for_each_entry(t, &msg->transfers, transfer_list) { + ret = spi_rw_sync(spi, t->tx_buf, t->rx_buf, t->len); - *retlen = m.actual_length - m25p_cmdsz(flash); - } else { - u32 i; + if (ret < 0) { + break; + } - /* the size of data remaining on the first page */ - page_size = flash->page_size - page_offset; + len += t->len; + } - t[1].len = page_size; - spi_sync(flash->spi, &m); + msg->actual_length = len; - *retlen = m.actual_length - m25p_cmdsz(flash); + spi_qup_stop(spi); + } + else { + ret = spi_sync(spi, msg); + } - /* write everything in flash->page_size chunks */ - for (i = page_size; i < len; i += page_size) { - page_size = len - i; - if (page_size > flash->page_size) - page_size = flash->page_size; + return ret; +} - /* write the next page to flash */ - m25p_addr2cmd(flash, to + i, flash->command); +#define spi_write_then_read avm_spi_write_then_read +#define spi_write avm_spi_write +#define spi_sync avm_spi_sync +#endif - t[1].tx_buf = buf + i; - t[1].len = page_size; +static int m25p80_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len) +{ + struct m25p *flash = nor->priv; + struct spi_device *spi = flash->spi; + int ret; + + ret = spi_write_then_read(spi, &code, 1, val, len); + if (ret < 0) + dev_err(&spi->dev, "error %d reading %x\n", ret, code); - wait_till_ready(flash); + return ret; +} - write_enable(flash); +static void m25p_addr2cmd(struct spi_nor *nor, unsigned int addr, u8 *cmd) +{ + /* opcode is in cmd[0] */ + cmd[1] = addr >> (nor->addr_width * 8 - 8); + cmd[2] = addr >> (nor->addr_width * 8 - 16); + cmd[3] = addr >> (nor->addr_width * 8 - 24); + cmd[4] = addr >> (nor->addr_width * 8 - 32); +} - spi_sync(flash->spi, &m); +static int m25p_cmdsz(struct spi_nor *nor) +{ + return 1 + nor->addr_width; +} - *retlen += m.actual_length - m25p_cmdsz(flash); - } - } +static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) +{ + struct m25p *flash = nor->priv; + struct spi_device *spi = flash->spi; - mutex_unlock(&flash->lock); + flash->command[0] = opcode; + if (buf) + memcpy(&flash->command[1], buf, len); - return 0; + return spi_write(spi, flash->command, len + 1); } -static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const u_char *buf) +static void m25p80_write(struct spi_nor *nor, loff_t to, size_t len, + size_t *retlen, const u_char *buf) { - struct m25p *flash = mtd_to_m25p(mtd); - struct spi_transfer t[2]; + struct m25p *flash = nor->priv; + struct spi_device *spi = flash->spi; + struct spi_transfer t[2] = {}; struct spi_message m; - size_t actual; - int cmd_sz, ret; - - pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev), - __func__, (u32)to, len); + int cmd_sz = m25p_cmdsz(nor); spi_message_init(&m); - memset(t, 0, (sizeof t)); + + if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) + cmd_sz = 1; + + flash->command[0] = nor->program_opcode; + m25p_addr2cmd(nor, to, flash->command); t[0].tx_buf = flash->command; - t[0].len = m25p_cmdsz(flash); + t[0].len = cmd_sz; spi_message_add_tail(&t[0], &m); t[1].tx_buf = buf; + t[1].len = len; spi_message_add_tail(&t[1], &m); - mutex_lock(&flash->lock); - - /* Wait until finished previous write command. */ - ret = wait_till_ready(flash); - if (ret) - goto time_out; - - write_enable(flash); + spi_sync(spi, &m); - actual = to % 2; - /* Start write from odd address. */ - if (actual) { - flash->command[0] = OPCODE_BP; - m25p_addr2cmd(flash, to, flash->command); - - /* write one byte. */ - t[1].len = 1; - spi_sync(flash->spi, &m); - ret = wait_till_ready(flash); - if (ret) - goto time_out; - *retlen += m.actual_length - m25p_cmdsz(flash); - } - to += actual; - - flash->command[0] = OPCODE_AAI_WP; - m25p_addr2cmd(flash, to, flash->command); - - /* Write out most of the data here. */ - cmd_sz = m25p_cmdsz(flash); - for (; actual < len - 1; actual += 2) { - t[0].len = cmd_sz; - /* write two bytes. */ - t[1].len = 2; - t[1].tx_buf = buf + actual; - - spi_sync(flash->spi, &m); - ret = wait_till_ready(flash); - if (ret) - goto time_out; - *retlen += m.actual_length - cmd_sz; - cmd_sz = 1; - to += 2; - } - write_disable(flash); - ret = wait_till_ready(flash); - if (ret) - goto time_out; - - /* Write out trailing byte if it exists. */ - if (actual != len) { - write_enable(flash); - flash->command[0] = OPCODE_BP; - m25p_addr2cmd(flash, to, flash->command); - t[0].len = m25p_cmdsz(flash); - t[1].len = 1; - t[1].tx_buf = buf + actual; - - spi_sync(flash->spi, &m); - ret = wait_till_ready(flash); - if (ret) - goto time_out; - *retlen += m.actual_length - m25p_cmdsz(flash); - write_disable(flash); - } - -time_out: - mutex_unlock(&flash->lock); - return ret; + *retlen += m.actual_length - cmd_sz; } -static int m25p80_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) +static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor) { - struct m25p *flash = mtd_to_m25p(mtd); - uint32_t offset = ofs; - uint8_t status_old, status_new; - int res = 0; - - mutex_lock(&flash->lock); - /* Wait until finished previous command */ - if (wait_till_ready(flash)) { - res = 1; - goto err; - } - - status_old = read_sr(flash); - - if (offset < flash->mtd.size-(flash->mtd.size/2)) - status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0; - else if (offset < flash->mtd.size-(flash->mtd.size/4)) - status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1; - else if (offset < flash->mtd.size-(flash->mtd.size/8)) - status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0; - else if (offset < flash->mtd.size-(flash->mtd.size/16)) - status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2; - else if (offset < flash->mtd.size-(flash->mtd.size/32)) - status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0; - else if (offset < flash->mtd.size-(flash->mtd.size/64)) - status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1; - else - status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0; - - /* Only modify protection if it will not unlock other areas */ - if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) > - (status_old&(SR_BP2|SR_BP1|SR_BP0))) { - write_enable(flash); - if (write_sr(flash, status_new) < 0) { - res = 1; - goto err; - } + switch (nor->flash_read) { + case SPI_NOR_DUAL: + return 2; + case SPI_NOR_QUAD: + return 4; + default: + return 0; } - -err: mutex_unlock(&flash->lock); - return res; } -static int m25p80_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) +/* + * Read an address range from the nor chip. The address range + * may be any size provided it is within the physical boundaries. + */ +static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len, + size_t *retlen, u_char *buf) { - struct m25p *flash = mtd_to_m25p(mtd); - uint32_t offset = ofs; - uint8_t status_old, status_new; - int res = 0; - - mutex_lock(&flash->lock); - /* Wait until finished previous command */ - if (wait_till_ready(flash)) { - res = 1; - goto err; - } + struct m25p *flash = nor->priv; + struct spi_device *spi = flash->spi; + struct spi_transfer t[2]; + struct spi_message m; + unsigned int dummy = nor->read_dummy; - status_old = read_sr(flash); + /* convert the dummy cycles to the number of bytes */ + dummy /= 8; - if (offset+len > flash->mtd.size-(flash->mtd.size/64)) - status_new = status_old & ~(SR_BP2|SR_BP1|SR_BP0); - else if (offset+len > flash->mtd.size-(flash->mtd.size/32)) - status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0; - else if (offset+len > flash->mtd.size-(flash->mtd.size/16)) - status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1; - else if (offset+len > flash->mtd.size-(flash->mtd.size/8)) - status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0; - else if (offset+len > flash->mtd.size-(flash->mtd.size/4)) - status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2; - else if (offset+len > flash->mtd.size-(flash->mtd.size/2)) - status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0; - else - status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1; + spi_message_init(&m); + memset(t, 0, (sizeof t)); - /* Only modify protection if it will not lock other areas */ - if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) < - (status_old&(SR_BP2|SR_BP1|SR_BP0))) { - write_enable(flash); - if (write_sr(flash, status_new) < 0) { - res = 1; - goto err; - } - } + flash->command[0] = nor->read_opcode; + m25p_addr2cmd(nor, from, flash->command); -err: mutex_unlock(&flash->lock); - return res; -} + if (dummy == 1) + t[0].dummy = true; -/****************************************************************************/ + t[0].type = SPI_TRANSFER_FLASH_READ_CMD; + t[0].tx_buf = flash->command; + t[0].len = m25p_cmdsz(nor) + dummy; + spi_message_add_tail(&t[0], &m); -/* - * SPI device driver setup and teardown - */ + t[1].type = SPI_TRANSFER_FLASH_READ_DATA; + t[1].rx_buf = buf; + t[1].rx_nbits = m25p80_rx_nbits(nor); + t[1].len = len; + spi_message_add_tail(&t[1], &m); -struct flash_info { - /* JEDEC id zero means "no ID" (most older chips); otherwise it has - * a high byte of zero plus three data bytes: the manufacturer id, - * then a two byte device id. - */ - u32 jedec_id; - u16 ext_id; + spi_sync(spi, &m); - /* The size listed here is what works with OPCODE_SE, which isn't - * necessarily called a "sector" by the vendor. - */ - unsigned sector_size; - u16 n_sectors; + *retlen = m.actual_length - m25p_cmdsz(nor) - dummy; + return 0; +} - u16 page_size; - u16 addr_width; +static int m25p80_erase(struct spi_nor *nor, loff_t offset) +{ + struct m25p *flash = nor->priv; - u16 flags; -#define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ -#define M25P_NO_ERASE 0x02 /* No erase command needed */ -#define SST_WRITE 0x04 /* use SST byte programming */ -}; + dev_dbg(nor->dev, "%dKiB at 0x%08x\n", + flash->spi_nor.mtd.erasesize / 1024, (u32)offset); -#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ - ((kernel_ulong_t)&(struct flash_info) { \ - .jedec_id = (_jedec_id), \ - .ext_id = (_ext_id), \ - .sector_size = (_sector_size), \ - .n_sectors = (_n_sectors), \ - .page_size = 256, \ - .flags = (_flags), \ - }) - -#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width) \ - ((kernel_ulong_t)&(struct flash_info) { \ - .sector_size = (_sector_size), \ - .n_sectors = (_n_sectors), \ - .page_size = (_page_size), \ - .addr_width = (_addr_width), \ - .flags = M25P_NO_ERASE, \ - }) - -/* NOTE: double check command sets and memory organization when you add - * more flash chips. This current list focusses on newer chips, which - * have been converging on command sets which including JEDEC ID. - */ -static const struct spi_device_id m25p_ids[] = { - /* Atmel -- some are (confusingly) marketed as "DataFlash" */ - { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, - { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, - - { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, - { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, - { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, - - { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, - { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, - { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, - { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, - - { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, - - /* EON -- en25xxx */ - { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, - { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, - { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, - { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, - { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, - { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) }, - - /* Everspin */ - { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2) }, - - /* GigaDevice */ - { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) }, - { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) }, - - /* Intel/Numonyx -- xxxs33b */ - { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, - { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, - { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, - - /* Macronix */ - { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, - { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, - { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, - { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, - { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) }, - { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) }, - { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, - { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, - { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) }, - { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, - { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, 0) }, - - /* Micron */ - { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) }, - { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) }, - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) }, - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) }, + /* Set up command buffer. */ + flash->command[0] = nor->erase_opcode; + m25p_addr2cmd(nor, offset, flash->command); - /* Spansion -- single (large) sector size only, at least - * for the chips listed here (without boot sectors). - */ - { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 0) }, - { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) }, - { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) }, - { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) }, - { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) }, - { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, - { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, - { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, - { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) }, - { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) }, - { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, - { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, - { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, - { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, - { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, - { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) }, - { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, - - /* SST -- large erase sizes are "overlays", "sectors" are 4K */ - { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, - { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, - { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, - { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, - { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, - { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, - { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, - { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, - { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, - - /* ST Microelectronics -- newer production may have feature updates */ - { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, - { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, - { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, - { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, - { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, - { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, - { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, - { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, - { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, - { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) }, - - { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) }, - { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) }, - { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) }, - { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) }, - { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) }, - { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) }, - { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) }, - { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) }, - { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) }, - - { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, - { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, - { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, - - { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) }, - { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, - { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, - - { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) }, - { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) }, - { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) }, - { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, - - /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ - { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, - { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, - { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, - { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, - { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, - { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, - { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, - { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) }, - { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, - { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, - { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, - { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, - { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, - { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) }, - - /* Catalyst / On Semiconductor -- non-JEDEC */ - { "cat25c11", CAT25_INFO( 16, 8, 16, 1) }, - { "cat25c03", CAT25_INFO( 32, 8, 16, 2) }, - { "cat25c09", CAT25_INFO( 128, 8, 32, 2) }, - { "cat25c17", CAT25_INFO( 256, 8, 32, 2) }, - { "cat25128", CAT25_INFO(2048, 8, 64, 2) }, - { }, -}; -MODULE_DEVICE_TABLE(spi, m25p_ids); + spi_write(flash->spi, flash->command, m25p_cmdsz(nor)); -static const struct spi_device_id *jedec_probe(struct spi_device *spi) -{ - int tmp; - u8 code = OPCODE_RDID; - u8 id[5]; - u32 jedec; - u16 ext_jedec; - struct flash_info *info; - - /* JEDEC also defines an optional "extended device information" - * string for after vendor-specific data, after the three bytes - * we use here. Supporting some chips might require using it. - */ - tmp = spi_write_then_read(spi, &code, 1, id, 5); - if (tmp < 0) { - pr_debug("%s: error %d reading JEDEC ID\n", - dev_name(&spi->dev), tmp); - return ERR_PTR(tmp); - } - jedec = id[0]; - jedec = jedec << 8; - jedec |= id[1]; - jedec = jedec << 8; - jedec |= id[2]; - - ext_jedec = id[3] << 8 | id[4]; - - for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) { - info = (void *)m25p_ids[tmp].driver_data; - if (info->jedec_id == jedec) { - if (info->ext_id != 0 && info->ext_id != ext_jedec) - continue; - return &m25p_ids[tmp]; - } - } - dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec); - return ERR_PTR(-ENODEV); + return 0; } - /* * board specific setup should have ensured the SPI clock used here * matches what the READ command supports, at least until this driver @@ -902,177 +565,69 @@ */ static int m25p_probe(struct spi_device *spi) { - const struct spi_device_id *id = spi_get_device_id(spi); - struct flash_platform_data *data; - struct m25p *flash; - struct flash_info *info; - unsigned i; struct mtd_part_parser_data ppdata; - struct device_node __maybe_unused *np = spi->dev.of_node; - -#ifdef CONFIG_MTD_OF_PARTS - if (!of_device_is_available(np)) - return -ENODEV; -#endif - - /* Platform data helps sort out which chip type we have, as - * well as how this board partitions it. If we don't have - * a chip ID, try the JEDEC id commands; they'll work for most - * newer chips, even if we don't recognize the particular chip. - */ - data = spi->dev.platform_data; - if (data && data->type) { - const struct spi_device_id *plat_id; - - for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) { - plat_id = &m25p_ids[i]; - if (strcmp(data->type, plat_id->name)) - continue; - break; - } - - if (i < ARRAY_SIZE(m25p_ids) - 1) - id = plat_id; - else - dev_warn(&spi->dev, "unrecognized id %s\n", data->type); - } - - info = (void *)id->driver_data; - - if (info->jedec_id) { - const struct spi_device_id *jid; + struct flash_platform_data *data; + struct m25p *flash; + struct spi_nor *nor; + enum read_mode mode = SPI_NOR_NORMAL; + char *flash_name = NULL; + int ret; - jid = jedec_probe(spi); - if (IS_ERR(jid)) { - return PTR_ERR(jid); - } else if (jid != id) { - /* - * JEDEC knows better, so overwrite platform ID. We - * can't trust partitions any longer, but we'll let - * mtd apply them anyway, since some partitions may be - * marked read-only, and we don't want to lose that - * information, even if it's not 100% accurate. - */ - dev_warn(&spi->dev, "found %s, expected %s\n", - jid->name, id->name); - id = jid; - info = (void *)jid->driver_data; - } - } + data = dev_get_platdata(&spi->dev); - flash = kzalloc(sizeof *flash, GFP_KERNEL); + flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL); if (!flash) return -ENOMEM; - flash->command = kmalloc(MAX_CMD_SIZE + (flash->fast_read ? 1 : 0), - GFP_KERNEL); - if (!flash->command) { - kfree(flash); - return -ENOMEM; - } - flash->spi = spi; - mutex_init(&flash->lock); - dev_set_drvdata(&spi->dev, flash); + nor = &flash->spi_nor; - /* - * Atmel, SST and Intel/Numonyx serial flash tend to power - * up with the software protection bits set - */ + /* install the hooks */ + nor->read = m25p80_read; + nor->write = m25p80_write; + nor->erase = m25p80_erase; + nor->write_reg = m25p80_write_reg; + nor->read_reg = m25p80_read_reg; + + nor->dev = &spi->dev; + nor->flash_node = spi->dev.of_node; + nor->priv = flash; - if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL || - JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL || - JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) { - write_enable(flash); - write_sr(flash, 0); - } + spi_set_drvdata(spi, flash); + flash->spi = spi; - if (data && data->name) - flash->mtd.name = data->name; - else - flash->mtd.name = dev_name(&spi->dev); + if (spi->mode & SPI_RX_QUAD) + mode = SPI_NOR_QUAD; + else if (spi->mode & SPI_RX_DUAL) + mode = SPI_NOR_DUAL; - flash->mtd.type = MTD_NORFLASH; - flash->mtd.writesize = 1; - flash->mtd.flags = MTD_CAP_NORFLASH; - flash->mtd.size = info->sector_size * info->n_sectors; - flash->mtd._erase = m25p80_erase; - flash->mtd._read = m25p80_read; - - /* flash protection support for STmicro chips */ - if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) { - flash->mtd._lock = m25p80_lock; - flash->mtd._unlock = m25p80_unlock; - } + if (data && data->name) + nor->mtd.name = data->name; - /* sst flash chips use AAI word program */ - if (info->flags & SST_WRITE) - flash->mtd._write = sst_write; + /* For some (historical?) reason many platforms provide two different + * names in flash_platform_data: "name" and "type". Quite often name is + * set to "m25p80" and then "type" provides a real chip name. + * If that's the case, respect "type" and ignore a "name". + */ + if (data && data->type) + flash_name = data->type; else - flash->mtd._write = m25p80_write; + flash_name = spi->modalias; - /* prefer "small sector" erase if possible */ - if (info->flags & SECT_4K) { - flash->erase_opcode = OPCODE_BE_4K; - flash->mtd.erasesize = 4096; - } else { - flash->erase_opcode = OPCODE_SE; - flash->mtd.erasesize = info->sector_size; - } - - if (info->flags & M25P_NO_ERASE) - flash->mtd.flags |= MTD_NO_ERASE; + ret = spi_nor_scan(nor, flash_name, mode); + if (ret) + return ret; + memset(&ppdata, '\0', sizeof(ppdata)); ppdata.of_node = spi->dev.of_node; - flash->mtd.dev.parent = &spi->dev; - flash->page_size = info->page_size; - flash->mtd.writebufsize = flash->page_size; - - flash->fast_read = false; -#ifdef CONFIG_OF - if (np && of_property_read_bool(np, "m25p,fast-read")) - flash->fast_read = true; -#endif -#ifdef CONFIG_M25PXX_USE_FAST_READ - flash->fast_read = true; +// AVM +#if defined(CONFIG_TFFS_DEV_LEGACY) && IS_ENABLED(CONFIG_TFFS_PANIC_LOG) + TFFS3_Register_Panic_CB(&flash->spi_nor.mtd, panic_reinit); #endif - if (info->addr_width) - flash->addr_width = info->addr_width; - else { - /* enable 4-byte addressing if the device exceeds 16MiB */ - if (flash->mtd.size > 0x1000000) { - flash->addr_width = 4; - set_4byte(flash, info->jedec_id, 1); - } else - flash->addr_width = 3; - } - - dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name, - (long long)flash->mtd.size >> 10); - - pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) " - ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", - flash->mtd.name, - (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20), - flash->mtd.erasesize, flash->mtd.erasesize / 1024, - flash->mtd.numeraseregions); - - if (flash->mtd.numeraseregions) - for (i = 0; i < flash->mtd.numeraseregions; i++) - pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, " - ".erasesize = 0x%.8x (%uKiB), " - ".numblocks = %d }\n", - i, (long long)flash->mtd.eraseregions[i].offset, - flash->mtd.eraseregions[i].erasesize, - flash->mtd.eraseregions[i].erasesize / 1024, - flash->mtd.eraseregions[i].numblocks); - - - /* partitions should match sector boundaries; and it may be good to - * use readonly partitions for writeprotected sectors (BP2..BP0). - */ - return mtd_device_parse_register(&flash->mtd, NULL, &ppdata, + return mtd_device_parse_register(&nor->mtd, + data ? data->part_probes : NULL, + &ppdata, data ? data->parts : NULL, data ? data->nr_parts : 0); } @@ -1080,27 +635,84 @@ static int m25p_remove(struct spi_device *spi) { - struct m25p *flash = dev_get_drvdata(&spi->dev); - int status; + struct m25p *flash = spi_get_drvdata(spi); /* Clean up MTD stuff. */ - status = mtd_device_unregister(&flash->mtd); - if (status == 0) { - kfree(flash->command); - kfree(flash); - } - return 0; + return mtd_device_unregister(&flash->spi_nor.mtd); +} + +static void m25p_shutdown(struct spi_device *spi) +{ + struct m25p *flash = spi_get_drvdata(spi); + + /* Ensure no pending flash operation in progress */ + spi_nor_wait_till_ready(&flash->spi_nor); } +/* + * Do NOT add to this array without reading the following: + * + * Historically, many flash devices are bound to this driver by their name. But + * since most of these flash are compatible to some extent, and their + * differences can often be differentiated by the JEDEC read-ID command, we + * encourage new users to add support to the spi-nor library, and simply bind + * against a generic string here (e.g., "jedec,spi-nor"). + * + * Many flash names are kept here in this list (as well as in spi-nor.c) to + * keep them available as module aliases for existing platforms. + */ +static const struct spi_device_id m25p_ids[] = { + /* + * Entries not used in DTs that should be safe to drop after replacing + * them with "nor-jedec" in platform data. + */ + {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"}, + + /* + * Entries that were used in DTs without "nor-jedec" fallback and should + * be kept for backward compatibility. + */ + {"at25df321a"}, {"at25df641"}, {"at26df081a"}, + {"mr25h256"}, + {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"}, + {"mx25l25635e"},{"mx66l51235l"}, + {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"}, + {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"}, + {"s25fl064k"}, + {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"}, + {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"}, + {"m25p64"}, {"m25p128"}, + {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"}, + {"w25q80bl"}, {"w25q128"}, {"w25q256"}, + + /* Flashes that can't be detected using JEDEC */ + {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"}, + {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"}, + {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"}, + + { }, +}; +MODULE_DEVICE_TABLE(spi, m25p_ids); + +static const struct of_device_id m25p_of_table[] = { + /* + * Generic compatibility for SPI NOR that can be identified by the + * JEDEC READ ID opcode (0x9F). Use this, if possible. + */ + { .compatible = "jedec,spi-nor" }, + {} +}; +MODULE_DEVICE_TABLE(of, m25p_of_table); static struct spi_driver m25p80_driver = { .driver = { .name = "m25p80", - .owner = THIS_MODULE, + .of_match_table = m25p_of_table, }, .id_table = m25p_ids, .probe = m25p_probe, .remove = m25p_remove, + .shutdown = m25p_shutdown, /* REVISIT: many of these chips have deep power-down modes, which * should clearly be entered on suspend() to minimize power use.