--- zzzz-none-000/linux-3.10.107/drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c 2017-06-27 09:49:32.000000000 +0000 +++ scorpion-7490-727/linux-3.10.107/drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c 2021-02-04 17:41:59.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Linux network driver for Brocade Converged Network Adapter. + * Linux network driver for QLogic BR-series Converged Network Adapter. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License (GPL) Version 2 as @@ -11,9 +11,10 @@ * General Public License for more details. */ /* - * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. + * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. + * Copyright (c) 2014-2015 QLogic Corporation * All rights reserved - * www.brocade.com + * www.qlogic.com */ #include "bfa_ioc.h" @@ -22,8 +23,7 @@ #include "bfi_reg.h" #include "bfa_defs.h" -#define bfa_ioc_ct_sync_pos(__ioc) \ - ((u32) (1 << bfa_ioc_pcifn(__ioc))) +#define bfa_ioc_ct_sync_pos(__ioc) BIT(bfa_ioc_pcifn(__ioc)) #define BFA_IOC_SYNC_REQD_SH 16 #define bfa_ioc_ct_get_sync_ackd(__val) (__val & 0x0000ffff) #define bfa_ioc_ct_clear_sync_ackd(__val) (__val & 0xffff0000) @@ -48,6 +48,12 @@ static void bfa_ioc_ct_sync_leave(struct bfa_ioc *ioc); static void bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc); static bool bfa_ioc_ct_sync_complete(struct bfa_ioc *ioc); +static void bfa_ioc_ct_set_cur_ioc_fwstate( + struct bfa_ioc *ioc, enum bfi_ioc_state fwstate); +static enum bfi_ioc_state bfa_ioc_ct_get_cur_ioc_fwstate(struct bfa_ioc *ioc); +static void bfa_ioc_ct_set_alt_ioc_fwstate( + struct bfa_ioc *ioc, enum bfi_ioc_state fwstate); +static enum bfi_ioc_state bfa_ioc_ct_get_alt_ioc_fwstate(struct bfa_ioc *ioc); static enum bfa_status bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode); static enum bfa_status bfa_ioc_ct2_pll_init(void __iomem *rb, @@ -68,6 +74,10 @@ .ioc_sync_leave = bfa_ioc_ct_sync_leave, .ioc_sync_ack = bfa_ioc_ct_sync_ack, .ioc_sync_complete = bfa_ioc_ct_sync_complete, + .ioc_set_fwstate = bfa_ioc_ct_set_cur_ioc_fwstate, + .ioc_get_fwstate = bfa_ioc_ct_get_cur_ioc_fwstate, + .ioc_set_alt_fwstate = bfa_ioc_ct_set_alt_ioc_fwstate, + .ioc_get_alt_fwstate = bfa_ioc_ct_get_alt_ioc_fwstate, }; static const struct bfa_ioc_hwif nw_hwif_ct2 = { @@ -85,6 +95,10 @@ .ioc_sync_leave = bfa_ioc_ct_sync_leave, .ioc_sync_ack = bfa_ioc_ct_sync_ack, .ioc_sync_complete = bfa_ioc_ct_sync_complete, + .ioc_set_fwstate = bfa_ioc_ct_set_cur_ioc_fwstate, + .ioc_get_fwstate = bfa_ioc_ct_get_cur_ioc_fwstate, + .ioc_set_alt_fwstate = bfa_ioc_ct_set_alt_ioc_fwstate, + .ioc_get_alt_fwstate = bfa_ioc_ct_get_alt_ioc_fwstate, }; /* Called from bfa_ioc_attach() to map asic specific calls. */ @@ -521,7 +535,7 @@ { u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync); - writel((r32 | bfa_ioc_ct_sync_pos(ioc)), ioc->ioc_regs.ioc_fail_sync); + writel(r32 | bfa_ioc_ct_sync_pos(ioc), ioc->ioc_regs.ioc_fail_sync); } static bool @@ -565,6 +579,32 @@ return false; } +static void +bfa_ioc_ct_set_cur_ioc_fwstate(struct bfa_ioc *ioc, + enum bfi_ioc_state fwstate) +{ + writel(fwstate, ioc->ioc_regs.ioc_fwstate); +} + +static enum bfi_ioc_state +bfa_ioc_ct_get_cur_ioc_fwstate(struct bfa_ioc *ioc) +{ + return (enum bfi_ioc_state)readl(ioc->ioc_regs.ioc_fwstate); +} + +static void +bfa_ioc_ct_set_alt_ioc_fwstate(struct bfa_ioc *ioc, + enum bfi_ioc_state fwstate) +{ + writel(fwstate, ioc->ioc_regs.alt_ioc_fwstate); +} + +static enum bfi_ioc_state +bfa_ioc_ct_get_alt_ioc_fwstate(struct bfa_ioc *ioc) +{ + return (enum bfi_ioc_state)readl(ioc->ioc_regs.alt_ioc_fwstate); +} + static enum bfa_status bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode) { @@ -626,7 +666,7 @@ writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0)); writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1)); } - r32 = readl((rb + PSS_CTL_REG)); + r32 = readl(rb + PSS_CTL_REG); r32 &= ~__PSS_LMEM_RESET; writel(r32, (rb + PSS_CTL_REG)); udelay(1000); @@ -637,7 +677,7 @@ writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG)); udelay(1000); - r32 = readl((rb + MBIST_STAT_REG)); + r32 = readl(rb + MBIST_STAT_REG); writel(0, (rb + MBIST_CTL_REG)); return BFA_STATUS_OK; } @@ -650,7 +690,7 @@ /* * put s_clk PLL and PLL FSM in reset */ - r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); + r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG); r32 &= ~(__APP_PLL_SCLK_ENABLE | __APP_PLL_SCLK_LRESETN); r32 |= (__APP_PLL_SCLK_ENARST | __APP_PLL_SCLK_BYPASS | __APP_PLL_SCLK_LOGIC_SOFT_RESET); @@ -658,30 +698,30 @@ /* * Ignore mode and program for the max clock (which is FC16) - * Firmware/NFC will do the PLL init appropiately + * Firmware/NFC will do the PLL init appropriately */ - r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); + r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG); r32 &= ~(__APP_PLL_SCLK_REFCLK_SEL | __APP_PLL_SCLK_CLK_DIV2); writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); /* * while doing PLL init dont clock gate ethernet subsystem */ - r32 = readl((rb + CT2_CHIP_MISC_PRG)); - writel((r32 | __ETH_CLK_ENABLE_PORT0), - (rb + CT2_CHIP_MISC_PRG)); - - r32 = readl((rb + CT2_PCIE_MISC_REG)); - writel((r32 | __ETH_CLK_ENABLE_PORT1), - (rb + CT2_PCIE_MISC_REG)); + r32 = readl(rb + CT2_CHIP_MISC_PRG); + writel(r32 | __ETH_CLK_ENABLE_PORT0, + rb + CT2_CHIP_MISC_PRG); + + r32 = readl(rb + CT2_PCIE_MISC_REG); + writel(r32 | __ETH_CLK_ENABLE_PORT1, + rb + CT2_PCIE_MISC_REG); /* * set sclk value */ - r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); + r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG); r32 &= (__P_SCLK_PLL_LOCK | __APP_PLL_SCLK_REFCLK_SEL | __APP_PLL_SCLK_CLK_DIV2); - writel(r32 | 0x1061731b, (rb + CT2_APP_PLL_SCLK_CTL_REG)); + writel(r32 | 0x1061731b, rb + CT2_APP_PLL_SCLK_CTL_REG); /* * poll for s_clk lock or delay 1ms @@ -702,28 +742,28 @@ /* * put l_clk PLL and PLL FSM in reset */ - r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); + r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); r32 &= ~(__APP_PLL_LCLK_ENABLE | __APP_PLL_LCLK_LRESETN); r32 |= (__APP_PLL_LCLK_ENARST | __APP_PLL_LCLK_BYPASS | __APP_PLL_LCLK_LOGIC_SOFT_RESET); - writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); + writel(r32, rb + CT2_APP_PLL_LCLK_CTL_REG); /* * set LPU speed (set for FC16 which will work for other modes) */ - r32 = readl((rb + CT2_CHIP_MISC_PRG)); + r32 = readl(rb + CT2_CHIP_MISC_PRG); writel(r32, (rb + CT2_CHIP_MISC_PRG)); /* * set LPU half speed (set for FC16 which will work for other modes) */ - r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); - writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); + r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); + writel(r32, rb + CT2_APP_PLL_LCLK_CTL_REG); /* * set lclk for mode (set for FC16) */ - r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); + r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); r32 &= (__P_LCLK_PLL_LOCK | __APP_LPUCLK_HALFSPEED); r32 |= 0x20c1731b; writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); @@ -739,14 +779,14 @@ { u32 r32; - r32 = readl((rb + PSS_CTL_REG)); + r32 = readl(rb + PSS_CTL_REG); r32 &= ~__PSS_LMEM_RESET; - writel(r32, (rb + PSS_CTL_REG)); + writel(r32, rb + PSS_CTL_REG); udelay(1000); - writel(__EDRAM_BISTR_START, (rb + CT2_MBIST_CTL_REG)); + writel(__EDRAM_BISTR_START, rb + CT2_MBIST_CTL_REG); udelay(1000); - writel(0, (rb + CT2_MBIST_CTL_REG)); + writel(0, rb + CT2_MBIST_CTL_REG); } static void @@ -760,22 +800,22 @@ /* * release soft reset on s_clk & l_clk */ - r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); - writel((r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET), - (rb + CT2_APP_PLL_SCLK_CTL_REG)); + r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG); + writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET, + rb + CT2_APP_PLL_SCLK_CTL_REG); /* * release soft reset on s_clk & l_clk */ - r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); - writel((r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET), - (rb + CT2_APP_PLL_LCLK_CTL_REG)); + r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); + writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET, + rb + CT2_APP_PLL_LCLK_CTL_REG); /* put port0, port1 MAC & AHB in reset */ - writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET), - (rb + CT2_CSI_MAC_CONTROL_REG(0))); - writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET), - (rb + CT2_CSI_MAC_CONTROL_REG(1))); + writel(__CSI_MAC_RESET | __CSI_MAC_AHB_RESET, + rb + CT2_CSI_MAC_CONTROL_REG(0)); + writel(__CSI_MAC_RESET | __CSI_MAC_AHB_RESET, + rb + CT2_CSI_MAC_CONTROL_REG(1)); } #define CT2_NFC_MAX_DELAY 1000 @@ -820,8 +860,8 @@ nfc_ver = readl(rb + CT2_RSC_GPR15_REG); - if ((wgn == (__A2T_AHB_LOAD | __WGN_READY)) && - (nfc_ver >= CT2_NFC_VER_VALID)) { + if (wgn == (__A2T_AHB_LOAD | __WGN_READY) && + nfc_ver >= CT2_NFC_VER_VALID) { if (bfa_ioc_ct2_nfc_halted(rb)) bfa_ioc_ct2_nfc_resume(rb); writel(__RESET_AND_START_SCLK_LCLK_PLLS, @@ -858,19 +898,19 @@ bfa_ioc_ct2_lclk_init(rb); /* release soft reset on s_clk & l_clk */ - r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); + r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG); writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + CT2_APP_PLL_SCLK_CTL_REG); - r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); + r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + CT2_APP_PLL_LCLK_CTL_REG); } /* Announce flash device presence, if flash was corrupted. */ if (wgn == (__WGN_READY | __GLBL_PF_VF_CFG_RDY)) { - r32 = readl((rb + PSS_GPIO_OUT_REG)); + r32 = readl(rb + PSS_GPIO_OUT_REG); writel(r32 & ~1, rb + PSS_GPIO_OUT_REG); - r32 = readl((rb + PSS_GPIO_OE_REG)); + r32 = readl(rb + PSS_GPIO_OE_REG); writel(r32 | 1, rb + PSS_GPIO_OE_REG); } @@ -878,27 +918,27 @@ * Mask the interrupts and clear any * pending interrupts left by BIOS/EFI */ - writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK)); - writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK)); + writel(1, rb + CT2_LPU0_HOSTFN_MBOX0_MSK); + writel(1, rb + CT2_LPU1_HOSTFN_MBOX0_MSK); /* For first time initialization, no need to clear interrupts */ r32 = readl(rb + HOST_SEM5_REG); if (r32 & 0x1) { - r32 = readl((rb + CT2_LPU0_HOSTFN_CMD_STAT)); + r32 = readl(rb + CT2_LPU0_HOSTFN_CMD_STAT); if (r32 == 1) { - writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT)); - readl((rb + CT2_LPU0_HOSTFN_CMD_STAT)); + writel(1, rb + CT2_LPU0_HOSTFN_CMD_STAT); + readl(rb + CT2_LPU0_HOSTFN_CMD_STAT); } - r32 = readl((rb + CT2_LPU1_HOSTFN_CMD_STAT)); + r32 = readl(rb + CT2_LPU1_HOSTFN_CMD_STAT); if (r32 == 1) { - writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT)); - readl((rb + CT2_LPU1_HOSTFN_CMD_STAT)); + writel(1, rb + CT2_LPU1_HOSTFN_CMD_STAT); + readl(rb + CT2_LPU1_HOSTFN_CMD_STAT); } } bfa_ioc_ct2_mem_init(rb); - writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG)); - writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG)); + writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC0_STATE_REG); + writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC1_STATE_REG); return BFA_STATUS_OK; }