--- zzzz-none-000/linux-3.10.107/drivers/pinctrl/pinctrl-tegra.h 2017-06-27 09:49:32.000000000 +0000 +++ scorpion-7490-727/linux-3.10.107/drivers/pinctrl/pinctrl-tegra.h 2021-02-04 17:41:59.000000000 +0000 @@ -72,108 +72,93 @@ */ struct tegra_function { const char *name; - const char * const *groups; + const char **groups; unsigned ngroups; }; /** * struct tegra_pingroup - Tegra pin group - * @mux_reg: Mux register offset. -1 if unsupported. - * @mux_bank: Mux register bank. 0 if unsupported. - * @mux_bit: Mux register bit. 0 if unsupported. - * @pupd_reg: Pull-up/down register offset. -1 if unsupported. - * @pupd_bank: Pull-up/down register bank. 0 if unsupported. - * @pupd_bit: Pull-up/down register bit. 0 if unsupported. - * @tri_reg: Tri-state register offset. -1 if unsupported. - * @tri_bank: Tri-state register bank. 0 if unsupported. - * @tri_bit: Tri-state register bit. 0 if unsupported. - * @einput_reg: Enable-input register offset. -1 if unsupported. - * @einput_bank: Enable-input register bank. 0 if unsupported. - * @einput_bit: Enable-input register bit. 0 if unsupported. - * @odrain_reg: Open-drain register offset. -1 if unsupported. - * @odrain_bank: Open-drain register bank. 0 if unsupported. - * @odrain_bit: Open-drain register bit. 0 if unsupported. - * @lock_reg: Lock register offset. -1 if unsupported. - * @lock_bank: Lock register bank. 0 if unsupported. - * @lock_bit: Lock register bit. 0 if unsupported. - * @ioreset_reg: IO reset register offset. -1 if unsupported. - * @ioreset_bank: IO reset register bank. 0 if unsupported. - * @ioreset_bit: IO reset register bit. 0 if unsupported. - * @rcv_sel_reg: Receiver select offset. -1 if unsupported. - * @rcv_sel_bank: Receiver select bank. 0 if unsupported. - * @rcv_sel_bit: Receiver select bit. 0 if unsupported. - * @drv_reg: Drive fields register offset. -1 if unsupported. - * This register contains the hsm, schmitt, lpmd, drvdn, - * drvup, slwr, and slwf parameters. - * @drv_bank: Drive fields register bank. 0 if unsupported. - * @hsm_bit: High Speed Mode register bit. 0 if unsupported. - * @schmitt_bit: Scmitt register bit. 0 if unsupported. - * @lpmd_bit: Low Power Mode register bit. 0 if unsupported. - * @drvdn_bit: Drive Down register bit. 0 if unsupported. - * @drvdn_width: Drive Down field width. 0 if unsupported. - * @drvup_bit: Drive Up register bit. 0 if unsupported. - * @drvup_width: Drive Up field width. 0 if unsupported. - * @slwr_bit: Slew Rising register bit. 0 if unsupported. - * @slwr_width: Slew Rising field width. 0 if unsupported. - * @slwf_bit: Slew Falling register bit. 0 if unsupported. - * @slwf_width: Slew Falling field width. 0 if unsupported. - * @drvtype_reg: Drive type fields register offset. -1 if unsupported. - * @drvtype_bank: Drive type fields register bank. 0 if unsupported. - * @drvtype_bit: Drive type register bit. 0 if unsupported. + * @name The name of the pin group. + * @pins An array of pin IDs included in this pin group. + * @npins The number of entries in @pins. + * @funcs The mux functions which can be muxed onto this group. + * @mux_reg: Mux register offset. + * This register contains the mux, einput, odrain, lock, + * ioreset, rcv_sel parameters. + * @mux_bank: Mux register bank. + * @mux_bit: Mux register bit. + * @pupd_reg: Pull-up/down register offset. + * @pupd_bank: Pull-up/down register bank. + * @pupd_bit: Pull-up/down register bit. + * @tri_reg: Tri-state register offset. + * @tri_bank: Tri-state register bank. + * @tri_bit: Tri-state register bit. + * @einput_bit: Enable-input register bit. + * @odrain_bit: Open-drain register bit. + * @lock_bit: Lock register bit. + * @ioreset_bit: IO reset register bit. + * @rcv_sel_bit: Receiver select bit. + * @drv_reg: Drive fields register offset. + * This register contains hsm, schmitt, lpmd, drvdn, + * drvup, slwr, slwf, and drvtype parameters. + * @drv_bank: Drive fields register bank. + * @hsm_bit: High Speed Mode register bit. + * @schmitt_bit: Scmitt register bit. + * @lpmd_bit: Low Power Mode register bit. + * @drvdn_bit: Drive Down register bit. + * @drvdn_width: Drive Down field width. + * @drvup_bit: Drive Up register bit. + * @drvup_width: Drive Up field width. + * @slwr_bit: Slew Rising register bit. + * @slwr_width: Slew Rising field width. + * @slwf_bit: Slew Falling register bit. + * @slwf_width: Slew Falling field width. + * @drvtype_bit: Drive type register bit. + * + * -1 in a *_reg field means that feature is unsupported for this group. + * *_bank and *_reg values are irrelevant when *_reg is -1. + * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature. * * A representation of a group of pins (possibly just one pin) in the Tegra * pin controller. Each group allows some parameter or parameters to be * configured. The most common is mux function selection. Many others exist * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex; * certain groups may only support configuring certain parameters, hence - * each parameter is optional, represented by a -1 "reg" value. + * each parameter is optional. */ struct tegra_pingroup { const char *name; const unsigned *pins; - unsigned npins; - unsigned funcs[4]; - unsigned func_safe; + u8 npins; + u8 funcs[4]; s16 mux_reg; s16 pupd_reg; s16 tri_reg; - s16 einput_reg; - s16 odrain_reg; - s16 lock_reg; - s16 ioreset_reg; - s16 rcv_sel_reg; s16 drv_reg; - s16 drvtype_reg; u32 mux_bank:2; u32 pupd_bank:2; u32 tri_bank:2; - u32 einput_bank:2; - u32 odrain_bank:2; - u32 ioreset_bank:2; - u32 rcv_sel_bank:2; - u32 lock_bank:2; u32 drv_bank:2; - u32 drvtype_bank:2; - u32 mux_bit:5; - u32 pupd_bit:5; - u32 tri_bit:5; - u32 einput_bit:5; - u32 odrain_bit:5; - u32 lock_bit:5; - u32 ioreset_bit:5; - u32 rcv_sel_bit:5; - u32 hsm_bit:5; - u32 schmitt_bit:5; - u32 lpmd_bit:5; - u32 drvdn_bit:5; - u32 drvup_bit:5; - u32 slwr_bit:5; - u32 slwf_bit:5; - u32 drvtype_bit:5; - u32 drvdn_width:6; - u32 drvup_width:6; - u32 slwr_width:6; - u32 slwf_width:6; + s32 mux_bit:6; + s32 pupd_bit:6; + s32 tri_bit:6; + s32 einput_bit:6; + s32 odrain_bit:6; + s32 lock_bit:6; + s32 ioreset_bit:6; + s32 rcv_sel_bit:6; + s32 hsm_bit:6; + s32 schmitt_bit:6; + s32 lpmd_bit:6; + s32 drvdn_bit:6; + s32 drvup_bit:6; + s32 slwr_bit:6; + s32 slwf_bit:6; + s32 drvtype_bit:6; + s32 drvdn_width:6; + s32 drvup_width:6; + s32 slwr_width:6; + s32 slwf_width:6; }; /** @@ -193,10 +178,13 @@ unsigned ngpios; const struct pinctrl_pin_desc *pins; unsigned npins; - const struct tegra_function *functions; + struct tegra_function *functions; unsigned nfunctions; const struct tegra_pingroup *groups; unsigned ngroups; + bool hsm_in_mux; + bool schmitt_in_mux; + bool drvtype_in_mux; }; int tegra_pinctrl_probe(struct platform_device *pdev,