--- zzzz-none-000/linux-3.10.107/drivers/pinctrl/sh-pfc/sh_pfc.h 2017-06-27 09:49:32.000000000 +0000 +++ scorpion-7490-727/linux-3.10.107/drivers/pinctrl/sh-pfc/sh_pfc.h 2021-02-04 17:41:59.000000000 +0000 @@ -11,33 +11,28 @@ #ifndef __SH_PFC_H #define __SH_PFC_H +#include +#include #include -#include - -typedef unsigned short pinmux_enum_t; - -#define SH_PFC_MARK_INVALID ((pinmux_enum_t)-1) enum { PINMUX_TYPE_NONE, - PINMUX_TYPE_FUNCTION, PINMUX_TYPE_GPIO, PINMUX_TYPE_OUTPUT, PINMUX_TYPE_INPUT, - PINMUX_TYPE_INPUT_PULLUP, - PINMUX_TYPE_INPUT_PULLDOWN, - - PINMUX_FLAG_TYPE, /* must be last */ }; #define SH_PFC_PIN_CFG_INPUT (1 << 0) #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) +#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) +#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) struct sh_pfc_pin { - const pinmux_enum_t enum_id; + u16 pin; + u16 enum_id; const char *name; unsigned int configs; }; @@ -57,6 +52,29 @@ unsigned int nr_pins; }; +/* + * Using union vin_data saves memory occupied by the VIN data pins. + * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups + * in this case. + */ +#define VIN_DATA_PIN_GROUP(n, s) \ + { \ + .name = #n#s, \ + .pins = n##_pins.data##s, \ + .mux = n##_mux.data##s, \ + .nr_pins = ARRAY_SIZE(n##_pins.data##s), \ + } + +union vin_data { + unsigned int data24[24]; + unsigned int data20[20]; + unsigned int data16[16]; + unsigned int data12[12]; + unsigned int data10[10]; + unsigned int data8[8]; + unsigned int data4[4]; +}; + #define SH_PFC_FUNCTION(n) \ { \ .name = #n, \ @@ -71,67 +89,60 @@ }; struct pinmux_func { - const pinmux_enum_t enum_id; + u16 enum_id; const char *name; }; -#define PINMUX_GPIO(gpio, data_or_mark) \ - [gpio] = { \ - .name = __stringify(gpio), \ - .enum_id = data_or_mark, \ - } -#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ - [gpio - (base)] = { \ - .name = __stringify(gpio), \ - .enum_id = data_or_mark, \ - } - -#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 - struct pinmux_cfg_reg { - unsigned long reg, reg_width, field_width; - const pinmux_enum_t *enum_ids; - const unsigned long *var_field_width; + u32 reg; + u8 reg_width, field_width; + const u16 *enum_ids; + const u8 *var_field_width; }; #define PINMUX_CFG_REG(name, r, r_width, f_width) \ .reg = r, .reg_width = r_width, .field_width = f_width, \ - .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) + .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ .reg = r, .reg_width = r_width, \ - .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \ - .enum_ids = (pinmux_enum_t []) + .var_field_width = (const u8 [r_width]) \ + { var_fw0, var_fwn, 0 }, \ + .enum_ids = (const u16 []) struct pinmux_data_reg { - unsigned long reg, reg_width; - const pinmux_enum_t *enum_ids; + u32 reg; + u8 reg_width; + const u16 *enum_ids; }; #define PINMUX_DATA_REG(name, r, r_width) \ .reg = r, .reg_width = r_width, \ - .enum_ids = (pinmux_enum_t [r_width]) \ + .enum_ids = (const u16 [r_width]) \ struct pinmux_irq { - int irq; - unsigned short *gpios; + const short *gpios; }; -#define PINMUX_IRQ(irq_nr, ids...) \ - { .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \ +#define PINMUX_IRQ(ids...) \ + { .gpios = (const short []) { ids, -1 } } struct pinmux_range { - pinmux_enum_t begin; - pinmux_enum_t end; - pinmux_enum_t force; + u16 begin; + u16 end; + u16 force; }; struct sh_pfc; struct sh_pfc_soc_operations { + int (*init)(struct sh_pfc *pfc); unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, unsigned int bias); + int (*get_io_voltage)(struct sh_pfc *pfc, unsigned int pin); + int (*set_io_voltage)(struct sh_pfc *pfc, unsigned int pin, + u16 voltage_mV); }; struct sh_pfc_soc_info { @@ -139,128 +150,205 @@ const struct sh_pfc_soc_operations *ops; struct pinmux_range input; - struct pinmux_range input_pd; - struct pinmux_range input_pu; struct pinmux_range output; struct pinmux_range function; const struct sh_pfc_pin *pins; unsigned int nr_pins; - const struct pinmux_range *ranges; - unsigned int nr_ranges; const struct sh_pfc_pin_group *groups; unsigned int nr_groups; const struct sh_pfc_function *functions; unsigned int nr_functions; +#ifdef CONFIG_SUPERH const struct pinmux_func *func_gpios; unsigned int nr_func_gpios; +#endif const struct pinmux_cfg_reg *cfg_regs; const struct pinmux_data_reg *data_regs; - const pinmux_enum_t *gpio_data; - unsigned int gpio_data_size; + const u16 *pinmux_data; + unsigned int pinmux_data_size; const struct pinmux_irq *gpio_irq; unsigned int gpio_irq_size; - unsigned long unlock_reg; + u32 unlock_reg; }; -enum { GPIO_CFG_REQ, GPIO_CFG_FREE }; +/* ----------------------------------------------------------------------------- + * Helper macros to create pin and port lists + */ + +/* + * sh_pfc_soc_info pinmux_data array macros + */ + +#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 + +#define PINMUX_IPSR_NOGP(ispr, fn) \ + PINMUX_DATA(fn##_MARK, FN_##fn) +#define PINMUX_IPSR_DATA(ipsr, fn) \ + PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) +#define PINMUX_IPSR_NOGM(ispr, fn, ms) \ + PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms) +#define PINMUX_IPSR_NOFN(ipsr, fn, ms) \ + PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms) +#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \ + PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn) + +/* + * GP port style (32 ports banks) + */ + +#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) fn(bank, pin, GP_##bank##_##pin, sfx, cfg) +#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) + +#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ + PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), PORT_GP_CFG_1(bank, 3, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), PORT_GP_CFG_1(bank, 7, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 8, fn, sfx, cfg), PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 22, fn, sfx, cfg), PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), PORT_GP_CFG_1(bank, 31, fn, sfx, cfg) +#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0) + +#define PORT_GP_32_REV(bank, fn, sfx) \ + PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ + PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ + PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ + PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ + PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ + PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ + PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ + PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ + PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ + PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ + PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ + PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ + PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ + PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ + PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ + PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) + +/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ +#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx +#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str) -/* helper macro for port */ -#define PORT_1(fn, pfx, sfx) fn(pfx, sfx) +/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ +#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \ + { \ + .pin = (bank * 32) + _pin, \ + .name = __stringify(_name), \ + .enum_id = _name##_DATA, \ + .configs = cfg, \ + } +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) + +/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ +#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) + +/* + * PORT style (linear pin space) + */ + +#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx) + +#define PORT_10(pn, fn, pfx, sfx) \ + PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \ + PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \ + PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \ + PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \ + PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx) + +#define PORT_90(pn, fn, pfx, sfx) \ + PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \ + PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \ + PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \ + PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \ + PORT_10(pn+90, fn, pfx##9, sfx) + +/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */ +#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx +#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) + +/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */ +#define PINMUX_GPIO(_pin) \ + [GPIO_##_pin] = { \ + .pin = (u16)-1, \ + .name = __stringify(GPIO_##_pin), \ + .enum_id = _pin##_DATA, \ + } + +/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ +#define SH_PFC_PIN_CFG(_pin, cfgs) \ + { \ + .pin = _pin, \ + .name = __stringify(PORT##_pin), \ + .enum_id = PORT##_pin##_DATA, \ + .configs = cfgs, \ + } + +/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */ +#define SH_PFC_PIN_NAMED(row, col, _name) \ + { \ + .pin = PIN_NUMBER(row, col), \ + .name = __stringify(PIN_##_name), \ + .configs = SH_PFC_PIN_CFG_NO_GPIO, \ + } -#define PORT_10(fn, pfx, sfx) \ - PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ - PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ - PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ - PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx) - -#define PORT_10_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ - PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ - PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ - PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) - -#define PORT_32(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_1(fn, pfx##31, sfx) - -#define PORT_32_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ - PORT_10_REV(fn, pfx, sfx) - -#define PORT_90(fn, pfx, sfx) \ - PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \ - PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \ - PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \ - PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \ - PORT_10(fn, pfx##9, sfx) - -#define _PORT_ALL(pfx, sfx) pfx##_##sfx -#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) -#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) -#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused) -#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) - -/* helper macro for pinmux_enum_t */ -#define PORT_DATA_I(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN) - -#define PORT_DATA_I_PD(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ - PORT##nr##_IN, PORT##nr##_IN_PD) - -#define PORT_DATA_I_PU(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ - PORT##nr##_IN, PORT##nr##_IN_PU) - -#define PORT_DATA_I_PU_PD(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ - PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) - -#define PORT_DATA_O(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT) - -#define PORT_DATA_IO(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ - PORT##nr##_IN) - -#define PORT_DATA_IO_PD(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ - PORT##nr##_IN, PORT##nr##_IN_PD) - -#define PORT_DATA_IO_PU(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ - PORT##nr##_IN, PORT##nr##_IN_PU) - -#define PORT_DATA_IO_PU_PD(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ - PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) - -/* helper macro for top 4 bits in PORTnCR */ -#define _PCRH(in, in_pd, in_pu, out) \ - 0, (out), (in), 0, \ - 0, 0, 0, 0, \ - 0, 0, (in_pd), 0, \ - 0, 0, (in_pu), 0 +/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, + * PORT_name_OUT, PORT_name_IN marks + */ +#define _PORT_DATA(pn, pfx, sfx) \ + PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \ + PORT##pfx##_OUT, PORT##pfx##_IN) +#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) + +/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */ +#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ + [gpio - (base)] = { \ + .name = __stringify(gpio), \ + .enum_id = data_or_mark, \ + } +#define GPIO_FN(str) \ + PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) +/* + * PORTnCR macro + */ #define PORTCR(nr, reg) \ { \ - PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ - _PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ - PORT##nr##_IN_PU, PORT##nr##_OUT), \ - PORT##nr##_FN0, PORT##nr##_FN1, \ - PORT##nr##_FN2, PORT##nr##_FN3, \ - PORT##nr##_FN4, PORT##nr##_FN5, \ - PORT##nr##_FN6, PORT##nr##_FN7 } \ + PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\ + /* PULMD[1:0], handled by .set_bias() */ \ + 0, 0, 0, 0, \ + /* IE and OE */ \ + 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ + /* SEC, not supported */ \ + 0, 0, \ + /* PTMD[2:0] */ \ + PORT##nr##_FN0, PORT##nr##_FN1, \ + PORT##nr##_FN2, PORT##nr##_FN3, \ + PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 \ + } \ } +/* + * GPIO number helper macro for R-Car + */ +#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin)) + #endif /* __SH_PFC_H */