--- zzzz-none-000/linux-2.6.32.61/arch/mips/include/asm/mipsmtregs.h 2013-06-10 09:43:48.000000000 +0000 +++ virian-300e-630/linux-2.6.32.61/arch/mips/include/asm/mipsmtregs.h 2013-04-23 11:18:38.000000000 +0000 @@ -28,14 +28,31 @@ #define read_c0_vpeconf0() __read_32bit_c0_register($1, 2) #define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val) +#define read_c0_vpeschedule() __read_32bit_c0_register($1, 5) +#define write_c0_vpeschedule(val) __write_32bit_c0_register($1, 5, val) + +#define read_c0_vpeschefback() __read_32bit_c0_register($1, 6) +#define write_c0_vpeschefback(val) __write_32bit_c0_register($1, 6, val) + +#define read_c0_vpeopt() __read_32bit_c0_register($1, 7) +#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val) + #define read_c0_tcstatus() __read_32bit_c0_register($2, 1) #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) #define read_c0_tcbind() __read_32bit_c0_register($2, 2) +#define write_c0_tcbind(val) __write_32bit_c0_register($2, 2, val) #define read_c0_tccontext() __read_32bit_c0_register($2, 5) #define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val) +#define read_c0_tcschedule() __read_32bit_c0_register($2, 6) +#define write_c0_tcschedule(val) __write_32bit_c0_register($2, 6, val) + +#define read_c0_tcschefback() __read_32bit_c0_register($2, 7) +#define write_c0_tcschefback(val) __write_32bit_c0_register($2, 7, val) + + #else /* Assembly */ /* * Macros for use in assembly language code @@ -47,13 +64,13 @@ #define CP0_VPECONTROL $1, 1 #define CP0_VPECONF0 $1, 2 #define CP0_VPECONF1 $1, 3 -#define CP0_YQMASK $1, 4 -#define CP0_VPESCHEDULE $1, 5 +#define CP0_YQMASK $1, 4 +#define CP0_VPESCHEDULE $1, 5 #define CP0_VPESCHEFBK $1, 6 #define CP0_TCSTATUS $2, 1 -#define CP0_TCBIND $2, 2 +#define CP0_TCBIND $2, 2 #define CP0_TCRESTART $2, 3 -#define CP0_TCHALT $2, 4 +#define CP0_TCHALT $2, 4 #define CP0_TCCONTEXT $2, 5 #define CP0_TCSCHEDULE $2, 6 #define CP0_TCSCHEFBK $2, 7 @@ -74,6 +91,10 @@ #define MVPCONTROL_STLB_SHIFT 2 #define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT) +#ifdef CONFIG_IFX_VPE_CACHE_SPLIT +#define MVPCONTROL_CPA_SHIFT 3 +#define MVPCONTROL_CPA (_ULCAST_(1) << MVPCONTROL_CPA_SHIFT) +#endif /* MVPConf0 fields */ #define MVPCONF0_PTC_SHIFT 0 @@ -84,6 +105,12 @@ #define MVPCONF0_TCA ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT) #define MVPCONF0_PTLBE_SHIFT 16 #define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT) + +#ifdef CONFIG_IFX_VPE_CACHE_SPLIT +#define MVPCONF0_PCP_SHIFT 27 +#define MVPCONF0_PCP (_ULCAST_(1) << MVPCONF0_PCP_SHIFT) +#endif + #define MVPCONF0_TLBS_SHIFT 29 #define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT) #define MVPCONF0_M_SHIFT 31 @@ -121,9 +148,31 @@ #define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT) #define VPECONF0_MVP_SHIFT 1 #define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT) + +#ifdef CONFIG_IFX_VPE_CACHE_SPLIT +#define VPECONF0_ICS_SHIFT 16 +#define VPECONF0_ICS (_ULCAST_(1) << VPECONF0_ICS_SHIFT) +#define VPECONF0_DCS_SHIFT 17 +#define VPECONF0_DCS (_ULCAST_(1) << VPECONF0_DCS_SHIFT) +#endif + #define VPECONF0_XTC_SHIFT 21 #define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT) +#ifdef CONFIG_IFX_VPE_CACHE_SPLIT +/* VPEOpt fields */ +#define VPEOPT_DWX_SHIFT 0 +#define VPEOPT_IWX_SHIFT 8 +#define VPEOPT_IWX0 ( _ULCAST_(0x1) << VPEOPT_IWX_SHIFT) +#define VPEOPT_IWX1 ( _ULCAST_(0x2) << VPEOPT_IWX_SHIFT) +#define VPEOPT_IWX2 ( _ULCAST_(0x4) << VPEOPT_IWX_SHIFT) +#define VPEOPT_IWX3 ( _ULCAST_(0x8) << VPEOPT_IWX_SHIFT) +#define VPEOPT_DWX0 ( _ULCAST_(0x1) << VPEOPT_DWX_SHIFT) +#define VPEOPT_DWX1 ( _ULCAST_(0x2) << VPEOPT_DWX_SHIFT) +#define VPEOPT_DWX2 ( _ULCAST_(0x4) << VPEOPT_DWX_SHIFT) +#define VPEOPT_DWX3 ( _ULCAST_(0x8) << VPEOPT_DWX_SHIFT) +#endif + /* TCStatus fields (per TC) */ #define TCSTATUS_TASID (_ULCAST_(0xff)) #define TCSTATUS_IXMT_SHIFT 10 @@ -350,6 +399,10 @@ #define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val) #define read_vpe_c0_vpeconf0() mftc0(1, 2) #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) +#define read_vpe_c0_vpeschedule() mftc0(1, 5) +#define write_vpe_c0_vpeschedule(val) mttc0(1, 5, val) +#define read_vpe_c0_vpeschefback() mftc0(1, 6) +#define write_vpe_c0_vpeschefback(val) mttc0(1, 6, val) #define read_vpe_c0_count() mftc0(9, 0) #define write_vpe_c0_count(val) mttc0(9, 0, val) #define read_vpe_c0_status() mftc0(12, 0) @@ -369,6 +422,10 @@ #define read_vpe_c0_epc() mftc0(14, 0) #define write_vpe_c0_epc(val) mttc0(14, 0, val) +#define read_vpe_c0_vpeopt() mftc0(1, 7) +#define write_vpe_c0_vpeopt(val) mttc0(1, 7, val) +#define read_vpe_c0_wired() mftc0(6, 0) +#define write_vpe_c0_wired(val) mttc0(6, 0, val) /* TC */ #define read_tc_c0_tcstatus() mftc0(2, 1) @@ -381,12 +438,19 @@ #define write_tc_c0_tchalt(val) mttc0(2, 4, val) #define read_tc_c0_tccontext() mftc0(2, 5) #define write_tc_c0_tccontext(val) mttc0(2, 5, val) - +#define read_tc_c0_tcschedule() mftc0(2, 6) +#define write_tc_c0_tcschedule(val) mttc0(2,6,val) +#define read_tc_c0_tcschefback() mftc0(2, 7) +#define write_tc_c0_tcschefback(val) mttc0(2,7,val) +#define read_tc_c0_entryhi() mftc0(10, 0) +#define write_tc_c0_entryhi(val) mttc0(10,0,val) + /* GPR */ #define read_tc_gpr_sp() mftgpr(29) #define write_tc_gpr_sp(val) mttgpr(29, val) #define read_tc_gpr_gp() mftgpr(28) #define write_tc_gpr_gp(val) mttgpr(28, val) +#define read_tc_gpr_ra() mftgpr(31) __BUILD_SET_C0(mvpcontrol)