/dts-v1/;
#include <linux/avm_hw_config_def.h>
#include <asm/mach-lantiq/common/ifx_gpio_def.h>
/ {
	avm-hw-revision{
		compatible = "avm,avm_hw_revision";
		revision = "192";
	};
	avm-gpio{
		compatible = "avm,avm_gpio_generic";
		gpio_avm_led_power{
			value = <0x103>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT>;
			module_id = <DEF_IFX_GPIO_MODULE_LED>;
		};
		gpio_avm_led_internet{
			value = <0x104>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT>;
			module_id = <DEF_IFX_GPIO_MODULE_LED>;
		};
		gpio_avm_led_festnetz{
			value = <0x105>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT>;
			module_id = <DEF_IFX_GPIO_MODULE_LED>;
		};
		gpio_avm_led_wlan{
			value = <0x106>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT>;
			module_id = <DEF_IFX_GPIO_MODULE_LED>;
		};
		gpio_avm_led_info{
			value = <0x107>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT>;
			module_id = <DEF_IFX_GPIO_MODULE_LED>;
		};
		gpio_avm_led_info_red{
			value = <0x102>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT>;
			module_id = <DEF_IFX_GPIO_MODULE_LED>;
		};
		gpio_avm_button_dect{
			value = <0>;
			param = <AVM_DEF_HW_PARAM_GPIO_IN_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_IN IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR>;
			module_id = <DEF_IFX_GPIO_MODULE_LED>;
		};
		gpio_avm_button_wlan{
			value = <1>;
			param = <AVM_DEF_HW_PARAM_GPIO_IN_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_IN IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_LED>;
		};
		gpio_avm_shift_led_st{
			value = <4>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR>;
			module_id = <DEF_IFX_GPIO_MODULE_SHIFT_REG>;
		};
		gpio_avm_shift_led_d{
			value = <5>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR>;
			module_id = <DEF_IFX_GPIO_MODULE_SHIFT_REG>;
		};
		gpio_avm_shift_led_sh{
			value = <6>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR>;
        	module_id = <DEF_IFX_GPIO_MODULE_SHIFT_REG>;
		};

		gpio_avm_dect_reset{
			value = <IFX_GPIO_PIN_ID(2,2)>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_PIGLET>;
		};
		gpio_avm_dect_uart_rx{
			value = <IFX_GPIO_PIN_ID(0,11)>;
			param = <AVM_DEF_HW_PARAM_NO_PARAM>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_IN IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR>;
			module_id = <DEF_IFX_GPIO_MODULE_PIGLET>;
		};
		gpio_avm_dect_uart_tx{
			value = <IFX_GPIO_PIN_ID(0,10)>;
			param = <AVM_DEF_HW_PARAM_NO_PARAM>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_PIGLET>;
		};
		gpio_avm_piglet_noemif_prog{
			value = <IFX_GPIO_PIN_ID(0,9)>;
			param = <AVM_DEF_HW_PARAM_NO_PARAM>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_FPGA>;
		};
		gpio_avm_piglet_noemif_clk{
			value = <IFX_GPIO_PIN_ID(0,8)>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_HIGH>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_FPGA>;
		};
		gpio_avm_piglet_noemif_data{
			value = <IFX_GPIO_PIN_ID(2,10)>;
			param = <AVM_DEF_HW_PARAM_NO_PARAM>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_FPGA>;
		};
		gpio_avm_piglet_noemif_done{
			value = <IFX_GPIO_PIN_ID(2,11)>;
			param = <AVM_DEF_HW_PARAM_GPIO_IN_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_IN IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_PUDEN_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_FPGA>;
		};
		gpio_avm_piglet_noemif_fpgaok{
			value = <IFX_GPIO_PIN_ID(2,3)>;
			param = <AVM_DEF_HW_PARAM_GPIO_IN_ACTIVE_HIGH>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_IN IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR>;
			module_id = <DEF_IFX_GPIO_MODULE_FPGA>;
		};
		gpio_avm_tdm_fsc{
			value = <IFX_GPIO_PIN_ID(3,10)>;
			param = <AVM_DEF_HW_PARAM_NO_PARAM>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_IN IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR>;
			module_id = <DEF_IFX_GPIO_MODULE_TDMCHECK>;
		};
		gpio_avm_tdm_dcl{
			value = <IFX_GPIO_PIN_ID(1,11)>;
			param = <AVM_DEF_HW_PARAM_NO_PARAM>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_IN IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR>;
			module_id = <DEF_IFX_GPIO_MODULE_TDMCHECK>;
		};
		gpio_avm_pcmlink_fsc{
			value = <IFX_GPIO_PIN_ID(3,10)>;
			param = <AVM_DEF_HW_PARAM_NO_PARAM>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_IN IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_SET IFX_GPIO_IOCTL_PIN_CONFIG_PUDSEL_SET IFX_GPIO_IOCTL_PIN_CONFIG_PUDEN_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_PCMLINK>;
		};
		gpio_avm_pcmlink_do{
			value = <IFX_GPIO_PIN_ID(1,9)>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_PCMLINK>;
		};
		gpio_avm_pcmlink_di{
			value = <IFX_GPIO_PIN_ID(1,10)>;
			param = <AVM_DEF_HW_PARAM_NO_PARAM>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_IN IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_SET IFX_GPIO_IOCTL_PIN_CONFIG_PUDSEL_SET IFX_GPIO_IOCTL_PIN_CONFIG_PUDEN_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_PCMLINK>;
		};
		gpio_avm_pcmlink_dcl{
			value = <IFX_GPIO_PIN_ID(1,11)>;
			param = <AVM_DEF_HW_PARAM_NO_PARAM>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_IN IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_PUDSEL_SET IFX_GPIO_IOCTL_PIN_CONFIG_PUDEN_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_PCMLINK>;
		};
		gpio_avm_spi_clk{
			value = <18>;
			param = <AVM_DEF_HW_PARAM_NO_PARAM>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_SSC>;
		};
		gpio_avm_spi_do{
			value = <17>;
			param = <AVM_DEF_HW_PARAM_NO_PARAM>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_SSC>;
		};
		gpio_avm_spi_di{
			value = <16>;
			param = <AVM_DEF_HW_PARAM_NO_PARAM>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_IN IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR>;
			module_id = <DEF_IFX_GPIO_MODULE_SSC>;
		};
		gpio_avm_spi_flash_cs{
			value = <15>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_HIGH>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_SPI_FLASH>;
		};
		gpio_avm_spi_usif_cs0{
			value = <14>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_HIGH>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_SET IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_SPI_FLASH>;
		};
		gpio_avm_spi_usif_clk{
			value = <19>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_HIGH>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_SPI_FLASH>;
		};
		gpio_avm_nand_ale{
			value = <13>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_NAND>;
		};
		gpio_avm_nand_cle{
			value = <24>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_NAND>;
		};
		gpio_avm_nand_rd_by{
			value = <48>;
			param = <AVM_DEF_HW_PARAM_GPIO_IN_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_IN IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_CLEAR>;
			module_id = <DEF_IFX_GPIO_MODULE_NAND>;
		};
		gpio_avm_nand_rd{
			value = <49>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_NAND>;
		};
		gpio_avm_nand_wr{
			value = <59>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_NAND>;
		};
		gpio_avm_nand_wp{
			value = <60>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_NAND>;
		};
		gpio_avm_nand_cs1{
			value = <23>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_NAND>;
		};
		gpio_avm_nand_d0{
			value = <51>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_NAND>;
		};
		gpio_avm_nand_d1{
			value = <50>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_NAND>;
		};
		gpio_avm_nand_d2{
			value = <52>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_NAND>;
		};
		gpio_avm_nand_d3{
			value = <57>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_NAND>;
		};
		gpio_avm_nand_d4{
			value = <56>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_NAND>;
		};
		gpio_avm_nand_d5{
			value = <55>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_NAND>;
		};
		gpio_avm_nand_d6{
			value = <54>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_NAND>;
		};
		gpio_avm_nand_d7{
			value = <53>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_NAND>;
		};
		gpio_avm_usb_pwr_en0{
			value = <0x101>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT>;
			module_id = <DEF_IFX_GPIO_MODULE_USB DEF_IFX_GPIO_MODULE_EARLY_REGISTER>;
		};
		gpio_avm_pll_clk{
			value = <3>;
			param = <AVM_DEF_HW_PARAM_NO_PARAM>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR>;
			module_id = <DEF_IFX_GPIO_MODULE_EXTPHY_MDIO>;
		};
		gpio_avm_pcie_reset0{
			value = <36>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_PCIE>;
		};
		gpio_avm_pcie_chip_reset0{
			value = <61>;
			param = <AVM_DEF_HW_PARAM_GPIO_OUT_ACTIVE_LOW>;
			config = <IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET>;
			module_id = <DEF_IFX_GPIO_MODULE_PCIE>;
		};
		pcie_disable_interface_1{
			value = <1>;
		};
	};
};