/** * Copyright (C) 2006-2014 Ikanos Communications. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. */ #ifndef __IKN_GPIO_REGS_H__ #define __IKN_GPIO_REGS_H__ #include "ikn_types.h" #define GPIO_BASE_ADDR 0xB9030000 typedef enum { eGPIO_MODE_NORMAL_INPUT = 0, //00 eGPIO_MODE_NORMAL_OUTPUT, //01 eGPIO_MODE_OPEN_DRAIN, //10 eGPIO_MODE_OPEN_SOURCE //11 }eGPIOMode_t; typedef enum { eGPIO_CLEAR = 0, eGPIO_SET = 1 }eGPIOBitVal_t; typedef enum { eGPIO_B_MIN = -1, eGPIO_B_0 = 0, eGPIO_B_1 = 1, eGPIO_B_2 = 2, eGPIO_B_3 = 3, eGPIO_B_4 = 4, eGPIO_B_5 = 5, eGPIO_B_6 = 6, eGPIO_B_7 = 7, eGPIO_B_8 = 8, eGPIO_B_9 = 9, eGPIO_B_10 = 10, eGPIO_B_11 = 11, eGPIO_B_12 = 12, eGPIO_B_13 = 13, eGPIO_B_14 = 14, eGPIO_B_15 = 15, eGPIO_B_16 = 16, eGPIO_B_17 = 17, eGPIO_B_18 = 18, eGPIO_B_19 = 19, eGPIO_B_20 = 20, eGPIO_B_21 = 21, eGPIO_B_22 = 22, eGPIO_B_23 = 23, eGPIO_B_24 = 24, eGPIO_B_25 = 25, eGPIO_B_26 = 26, eGPIO_B_27 = 27, eGPIO_B_28 = 28, eGPIO_B_29 = 29, eGPIO_B_30 = 30, eGPIO_B_31 = 31, eGPIO_B_MAX = 32 }eGPIOPins_t; /* * Following is the alternate function table * +-----------------------------------------------------------------+ * | | - | Input | * + GPIO_B_0 +---------------------------+-------------------------+ * | | SFLASH_CS | Output | * +-----------+---------------------------+-------------------------+ * | | - | Input | * + GPIO_B_1 +---------------------------+-------------------------+ * | | SFLASH_HOLD | Output | * +-----------+---------------------------+-------------------------+ * | | - | Input | * + GPIO_B_2 +---------------------------+-------------------------+ * | | SFLASH_WP | Output | * +-----------+---------------------------+-------------------------+ * | | SPI_SLV_CS | Input | * + GPIO_B_3 +---------------------------+-------------------------+ * | | | Output | * +-----------+---------------------------+-------------------------+ * | | - | Input | * + GPIO_B_4 +---------------------------+-------------------------+ * | | SPI_CS0_OUT | Output | * +-----------+---------------------------+-------------------------+ * | | - | Input | * + GPIO_B_5 +---------------------------+-------------------------+ * | | SPI_CS1_OUT | Output | * +-----------+---------------------------+-------------------------+ * | | - | Input | * + GPIO_B_6 +---------------------------+-------------------------+ * | | SPI_CS2_OUT | Output | * +-----------+---------------------------+-------------------------+ * | | - | Input | * + GPIO_B_7 +---------------------------+-------------------------+ * | | SPI_CS3_OUT | Output | * +-----------+---------------------------+-------------------------+ * | | - | Input | * + GPIO_B_8 +---------------------------+-------------------------+ * | | SPI_CS4_OUT | Output | * +-----------+---------------------------+-------------------------+ * | | - | Input | * + GPIO_B_9 +---------------------------+-------------------------+ * | | SPI_CS5_OUT | Output | * +-----------+---------------------------+-------------------------+ * | | - | Input | * + GPIO_B_10 +---------------------------+-------------------------+ * | | SPI_CS6_OUT | Output | * +-----------+---------------------------+-------------------------+ * | | - | Input | * + GPIO_B_11 +---------------------------+-------------------------+ * | | UART2_TXD | Output | * +-----------+---------------------------+-------------------------+ * | | UART2_RXD | Input | * + GPIO_B_12 +---------------------------+-------------------------+ * | | - | Output | * +-----------+---------------------------+-------------------------+ * | | - | Input | * + GPIO_B_13 +---------------------------+-------------------------+ * | | UART2_RTS | Output | * +-----------+---------------------------+-------------------------+ * | | UART2_CTS | Input | * + GPIO_B_14 +---------------------------+-------------------------+ * | | DSP_ELOUT | Output | * +-----------+---------------------------+-------------------------+ * | | SATA_MP_SWITCH | Input | * + GPIO_B_15 +---------------------------+-------------------------+ * | | DSP_NEMS | Output | * +-----------+---------------------------+-------------------------+ * | | SATA_CP_DETECT | Input | * + GPIO_B_16 +---------------------------+-------------------------+ * | | DSP_NEBG | Output | * +-----------+---------------------------+-------------------------+ * | | DSP_ECLK | Input | * + GPIO_B_17 +---------------------------+-------------------------+ * | | PLL_TEST (USB_REF_CLK, | Output | * | | AHB_CLK,FT_CLK,DSP_CLK) | | * +-----------+---------------------------+-------------------------+ * | | DSP_NERESET | Input | * + GPIO_B_18 +---------------------------+-------------------------+ * | | SATA_CP_POD | Output | * +-----------+---------------------------+-------------------------+ * | | DSP_EE | Input | * + GPIO_B_19 +---------------------------+-------------------------+ * | | DSP0_FP2S | Output | * +-----------+---------------------------+-------------------------+ * | | DSP_NEINT | Input | * + GPIO_B_20 +---------------------------+-------------------------+ * | | DSP0_PF3 | Output | * +-----------+---------------------------+-------------------------+ * | | DSP_NEBR | Input | * + GPIO_B_21 +---------------------------+-------------------------+ * | | DSP1_PF2 | Output | * +-----------+---------------------------+-------------------------+ * | | DSP_ELIN | Input | * + GPIO_B_22 +---------------------------+-------------------------+ * | | DSP_PF3 | Output | * +-----------+---------------------------+-------------------------+ * | | - | Input | * + GPIO_B_23 +---------------------------+-------------------------+ * | | GIGE0_AP_DEBUG | Output | * +-----------+---------------------------+-------------------------+ * | | INT[56]/TIMER0_ENABLE | Input | * + GPIO_B_24 +---------------------------+-------------------------+ * | | GIGIE1_AP_DEBUG | Output | * +-----------+---------------------------+-------------------------+ * | | INT[57]/TIMER1_ENABLE | Input | * + GPIO_B_25 +---------------------------+-------------------------+ * | | GIGE2/VAP_AP_DEBUG | Output | * +-----------+---------------------------+-------------------------+ * | | INT[58]/TIMER2_ENABLE | Input | * + GPIO_B_26 +---------------------------+-------------------------+ * | | CLASS1_AP_DEBUG | Output | * +-----------+---------------------------+-------------------------+ * | | INT[59]/TIMER3_ENABLE | Input | * + GPIO_B_27 +---------------------------+-------------------------+ * | | CLASS2_AP_DEBUG | Output | * +-----------+---------------------------+-------------------------+ * | | INT[60] | Input | * + GPIO_B_28 +---------------------------+-------------------------+ * | | BMU_AP_DEBUG | Output | * +-----------+---------------------------+-------------------------+ * | | INT[61] | Input | * + GPIO_B_29 +---------------------------+-------------------------+ * | | SPA_DEBUG | Output | * +-----------+---------------------------+-------------------------+ * | | INT[62]/DYING_GASP | Input | * + GPIO_B_30 +---------------------------+-------------------------+ * | | HAP_AP_DEBUG | Output | * +-----------+---------------------------+-------------------------+ * | | INT[63] | Input | * + GPIO_B_31 +---------------------------+-------------------------+ * | | - | Output | * +-----------+---------------------------+-------------------------+ */ typedef struct gpioRegs_s { reg32Bit regGPIOInput; //0xb9030000 reg32Bit regGPIOOutputSet; //0xb9030004 reg32Bit regGPIOOutputClear; //0xb9030008 reg32Bit regGPIOMode1; //0xb903000c reg32Bit regGPIOMode2; //0xb9030010 reg32Bit regGPIOAltFuncSel; //0xb9030014 reg32Bit regGPIODefAltFuncVal; //0xb9030018 }gpioRegs_t; #endif