--- zzzz-none-000/linux-3.10.107/arch/arm/mach-msm/devices-iommu.c 2017-06-27 09:49:32.000000000 +0000 +++ vr9-7490-729/linux-3.10.107/arch/arm/mach-msm/devices-iommu.c 2021-11-10 11:53:52.000000000 +0000 @@ -1,4 +1,4 @@ -/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -8,11 +8,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. */ #include @@ -21,6 +16,7 @@ #include #include #include +#include static struct resource msm_iommu_jpegd_resources[] = { { @@ -31,14 +27,14 @@ }, { .name = "nonsecure_irq", - .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ, - .end = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ, + .start = 98, + .end = 98, .flags = IORESOURCE_IRQ, }, { .name = "secure_irq", - .start = SMMU_JPEGD_CB_SC_SECURE_IRQ, - .end = SMMU_JPEGD_CB_SC_SECURE_IRQ, + .start = 97, + .end = 97, .flags = IORESOURCE_IRQ, }, }; @@ -52,14 +48,14 @@ }, { .name = "nonsecure_irq", - .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ, - .end = SMMU_VPE_CB_SC_NON_SECURE_IRQ, + .start = 84, + .end = 84, .flags = IORESOURCE_IRQ, }, { .name = "secure_irq", - .start = SMMU_VPE_CB_SC_SECURE_IRQ, - .end = SMMU_VPE_CB_SC_SECURE_IRQ, + .start = 83, + .end = 83, .flags = IORESOURCE_IRQ, }, }; @@ -73,14 +69,14 @@ }, { .name = "nonsecure_irq", - .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ, - .end = SMMU_MDP0_CB_SC_NON_SECURE_IRQ, + .start = 96, + .end = 96, .flags = IORESOURCE_IRQ, }, { .name = "secure_irq", - .start = SMMU_MDP0_CB_SC_SECURE_IRQ, - .end = SMMU_MDP0_CB_SC_SECURE_IRQ, + .start = 95, + .end = 95, .flags = IORESOURCE_IRQ, }, }; @@ -94,14 +90,14 @@ }, { .name = "nonsecure_irq", - .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ, - .end = SMMU_MDP1_CB_SC_NON_SECURE_IRQ, + .start = 94, + .end = 94, .flags = IORESOURCE_IRQ, }, { .name = "secure_irq", - .start = SMMU_MDP1_CB_SC_SECURE_IRQ, - .end = SMMU_MDP1_CB_SC_SECURE_IRQ, + .start = 93, + .end = 93, .flags = IORESOURCE_IRQ, }, }; @@ -115,14 +111,14 @@ }, { .name = "nonsecure_irq", - .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ, - .end = SMMU_ROT_CB_SC_NON_SECURE_IRQ, + .start = 92, + .end = 92, .flags = IORESOURCE_IRQ, }, { .name = "secure_irq", - .start = SMMU_ROT_CB_SC_SECURE_IRQ, - .end = SMMU_ROT_CB_SC_SECURE_IRQ, + .start = 91, + .end = 91, .flags = IORESOURCE_IRQ, }, }; @@ -136,14 +132,14 @@ }, { .name = "nonsecure_irq", - .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ, - .end = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ, + .start = 100, + .end = 100, .flags = IORESOURCE_IRQ, }, { .name = "secure_irq", - .start = SMMU_IJPEG_CB_SC_SECURE_IRQ, - .end = SMMU_IJPEG_CB_SC_SECURE_IRQ, + .start = 99, + .end = 99, .flags = IORESOURCE_IRQ, }, }; @@ -157,14 +153,14 @@ }, { .name = "nonsecure_irq", - .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ, - .end = SMMU_VFE_CB_SC_NON_SECURE_IRQ, + .start = 86, + .end = 86, .flags = IORESOURCE_IRQ, }, { .name = "secure_irq", - .start = SMMU_VFE_CB_SC_SECURE_IRQ, - .end = SMMU_VFE_CB_SC_SECURE_IRQ, + .start = 85, + .end = 85, .flags = IORESOURCE_IRQ, }, }; @@ -178,14 +174,14 @@ }, { .name = "nonsecure_irq", - .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ, - .end = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ, + .start = 90, + .end = 90, .flags = IORESOURCE_IRQ, }, { .name = "secure_irq", - .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ, - .end = SMMU_VCODEC_A_CB_SC_SECURE_IRQ, + .start = 89, + .end = 89, .flags = IORESOURCE_IRQ, }, }; @@ -199,14 +195,14 @@ }, { .name = "nonsecure_irq", - .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ, - .end = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ, + .start = 88, + .end = 88, .flags = IORESOURCE_IRQ, }, { .name = "secure_irq", - .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ, - .end = SMMU_VCODEC_B_CB_SC_SECURE_IRQ, + .start = 87, + .end = 87, .flags = IORESOURCE_IRQ, }, }; @@ -220,14 +216,35 @@ }, { .name = "nonsecure_irq", - .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ, - .end = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ, + .start = 102, + .end = 102, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = 101, + .end = 101, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msm_iommu_gfx3d1_resources[] = { + { + .start = 0x07D00000, + .end = 0x07D00000 + SZ_1M - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = 243, + .end = 243, .flags = IORESOURCE_IRQ, }, { .name = "secure_irq", - .start = SMMU_GFX3D_CB_SC_SECURE_IRQ, - .end = SMMU_GFX3D_CB_SC_SECURE_IRQ, + .start = 242, + .end = 242, .flags = IORESOURCE_IRQ, }, }; @@ -241,14 +258,14 @@ }, { .name = "nonsecure_irq", - .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ, - .end = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ, + .start = 104, + .end = 104, .flags = IORESOURCE_IRQ, }, { .name = "secure_irq", - .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ, - .end = SMMU_GFX2D0_CB_SC_SECURE_IRQ, + .start = 103, + .end = 103, .flags = IORESOURCE_IRQ, }, }; @@ -262,14 +279,35 @@ }, { .name = "nonsecure_irq", - .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, - .end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, + .start = 243, + .end = 243, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = 242, + .end = 242, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msm_iommu_vcap_resources[] = { + { + .start = 0x07200000, + .end = 0x07200000 + SZ_1M - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = 269, + .end = 269, .flags = IORESOURCE_IRQ, }, { .name = "secure_irq", - .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ, - .end = SMMU_GFX2D1_CB_SC_SECURE_IRQ, + .start = 268, + .end = 268, .flags = IORESOURCE_IRQ, }, }; @@ -327,16 +365,30 @@ static struct msm_iommu_dev gfx3d_iommu = { .name = "gfx3d", .ncb = 3, + .ttbr_split = 1, +}; + +static struct msm_iommu_dev gfx3d1_iommu = { + .name = "gfx3d1", + .ncb = 3, + .ttbr_split = 1, }; static struct msm_iommu_dev gfx2d0_iommu = { .name = "gfx2d0", .ncb = 2, + .ttbr_split = 1, }; static struct msm_iommu_dev gfx2d1_iommu = { .name = "gfx2d1", .ncb = 2, + .ttbr_split = 1, +}; + +static struct msm_iommu_dev vcap_iommu = { + .name = "vcap", + .ncb = 2, }; static struct platform_device msm_device_iommu_jpegd = { @@ -344,6 +396,7 @@ .id = 0, .dev = { .parent = &msm_root_iommu_dev.dev, + .platform_data = &jpegd_iommu, }, .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources), .resource = msm_iommu_jpegd_resources, @@ -354,6 +407,7 @@ .id = 1, .dev = { .parent = &msm_root_iommu_dev.dev, + .platform_data = &vpe_iommu, }, .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources), .resource = msm_iommu_vpe_resources, @@ -364,6 +418,7 @@ .id = 2, .dev = { .parent = &msm_root_iommu_dev.dev, + .platform_data = &mdp0_iommu, }, .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources), .resource = msm_iommu_mdp0_resources, @@ -374,6 +429,7 @@ .id = 3, .dev = { .parent = &msm_root_iommu_dev.dev, + .platform_data = &mdp1_iommu, }, .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources), .resource = msm_iommu_mdp1_resources, @@ -384,6 +440,7 @@ .id = 4, .dev = { .parent = &msm_root_iommu_dev.dev, + .platform_data = &rot_iommu, }, .num_resources = ARRAY_SIZE(msm_iommu_rot_resources), .resource = msm_iommu_rot_resources, @@ -394,6 +451,7 @@ .id = 5, .dev = { .parent = &msm_root_iommu_dev.dev, + .platform_data = &ijpeg_iommu, }, .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources), .resource = msm_iommu_ijpeg_resources, @@ -404,6 +462,7 @@ .id = 6, .dev = { .parent = &msm_root_iommu_dev.dev, + .platform_data = &vfe_iommu, }, .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources), .resource = msm_iommu_vfe_resources, @@ -414,6 +473,7 @@ .id = 7, .dev = { .parent = &msm_root_iommu_dev.dev, + .platform_data = &vcodec_a_iommu, }, .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources), .resource = msm_iommu_vcodec_a_resources, @@ -424,6 +484,7 @@ .id = 8, .dev = { .parent = &msm_root_iommu_dev.dev, + .platform_data = &vcodec_b_iommu, }, .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources), .resource = msm_iommu_vcodec_b_resources, @@ -434,31 +495,56 @@ .id = 9, .dev = { .parent = &msm_root_iommu_dev.dev, + .platform_data = &gfx3d_iommu, }, .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources), .resource = msm_iommu_gfx3d_resources, }; +static struct platform_device msm_device_iommu_gfx3d1 = { + .name = "msm_iommu", + .id = 10, + .dev = { + .parent = &msm_root_iommu_dev.dev, + .platform_data = &gfx3d1_iommu, + }, + .num_resources = ARRAY_SIZE(msm_iommu_gfx3d1_resources), + .resource = msm_iommu_gfx3d1_resources, +}; + static struct platform_device msm_device_iommu_gfx2d0 = { .name = "msm_iommu", .id = 10, .dev = { .parent = &msm_root_iommu_dev.dev, + .platform_data = &gfx2d0_iommu, }, .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources), .resource = msm_iommu_gfx2d0_resources, }; -struct platform_device msm_device_iommu_gfx2d1 = { +static struct platform_device msm_device_iommu_gfx2d1 = { .name = "msm_iommu", .id = 11, .dev = { .parent = &msm_root_iommu_dev.dev, + .platform_data = &gfx2d1_iommu, }, .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources), .resource = msm_iommu_gfx2d1_resources, }; +static struct platform_device msm_device_iommu_vcap = { + .name = "msm_iommu", + .id = 11, + .dev = { + .parent = &msm_root_iommu_dev.dev, + .platform_data = &vcap_iommu, + }, + .num_resources = ARRAY_SIZE(msm_iommu_vcap_resources), + .resource = msm_iommu_vcap_resources, +}; + static struct msm_iommu_ctx_dev jpegd_src_ctx = { .name = "jpegd_src", .num = 0, @@ -483,26 +569,26 @@ .mids = {1, -1} }; -static struct msm_iommu_ctx_dev mdp_vg1_ctx = { - .name = "mdp_vg1", +static struct msm_iommu_ctx_dev mdp_port0_cb0_ctx = { + .name = "mdp_port0_cb0", .num = 0, .mids = {0, 2, -1} }; -static struct msm_iommu_ctx_dev mdp_rgb1_ctx = { - .name = "mdp_rgb1", +static struct msm_iommu_ctx_dev mdp_port0_cb1_ctx = { + .name = "mdp_port0_cb1", .num = 1, .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1} }; -static struct msm_iommu_ctx_dev mdp_vg2_ctx = { - .name = "mdp_vg2", +static struct msm_iommu_ctx_dev mdp_port1_cb0_ctx = { + .name = "mdp_port1_cb0", .num = 0, .mids = {0, 2, -1} }; -static struct msm_iommu_ctx_dev mdp_rgb2_ctx = { - .name = "mdp_rgb2", +static struct msm_iommu_ctx_dev mdp_port1_cb1_ctx = { + .name = "mdp_port1_cb1", .num = 1, .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1} }; @@ -574,6 +660,19 @@ 31, -1} }; +static struct msm_iommu_ctx_dev gfx3d1_user_ctx = { + .name = "gfx3d1_user", + .num = 0, + .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} +}; + +static struct msm_iommu_ctx_dev gfx3d1_priv_ctx = { + .name = "gfx3d1_priv", + .num = 1, + .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, + 31, -1} +}; + static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = { .name = "gfx2d0_2d0", .num = 0, @@ -586,11 +685,24 @@ .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} }; +static struct msm_iommu_ctx_dev vcap_vc_ctx = { + .name = "vcap_vc", + .num = 0, + .mids = {0, -1} +}; + +static struct msm_iommu_ctx_dev vcap_vp_ctx = { + .name = "vcap_vp", + .num = 1, + .mids = {1, -1} +}; + static struct platform_device msm_device_jpegd_src_ctx = { .name = "msm_iommu_ctx", .id = 0, .dev = { .parent = &msm_device_iommu_jpegd.dev, + .platform_data = &jpegd_src_ctx, }, }; @@ -599,6 +711,7 @@ .id = 1, .dev = { .parent = &msm_device_iommu_jpegd.dev, + .platform_data = &jpegd_dst_ctx, }, }; @@ -607,6 +720,7 @@ .id = 2, .dev = { .parent = &msm_device_iommu_vpe.dev, + .platform_data = &vpe_src_ctx, }, }; @@ -615,38 +729,43 @@ .id = 3, .dev = { .parent = &msm_device_iommu_vpe.dev, + .platform_data = &vpe_dst_ctx, }, }; -static struct platform_device msm_device_mdp_vg1_ctx = { +static struct platform_device msm_device_mdp_port0_cb0_ctx = { .name = "msm_iommu_ctx", .id = 4, .dev = { .parent = &msm_device_iommu_mdp0.dev, + .platform_data = &mdp_port0_cb0_ctx, }, }; -static struct platform_device msm_device_mdp_rgb1_ctx = { +static struct platform_device msm_device_mdp_port0_cb1_ctx = { .name = "msm_iommu_ctx", .id = 5, .dev = { .parent = &msm_device_iommu_mdp0.dev, + .platform_data = &mdp_port0_cb1_ctx, }, }; -static struct platform_device msm_device_mdp_vg2_ctx = { +static struct platform_device msm_device_mdp_port1_cb0_ctx = { .name = "msm_iommu_ctx", .id = 6, .dev = { .parent = &msm_device_iommu_mdp1.dev, + .platform_data = &mdp_port1_cb0_ctx, }, }; -static struct platform_device msm_device_mdp_rgb2_ctx = { +static struct platform_device msm_device_mdp_port1_cb1_ctx = { .name = "msm_iommu_ctx", .id = 7, .dev = { .parent = &msm_device_iommu_mdp1.dev, + .platform_data = &mdp_port1_cb1_ctx, }, }; @@ -655,6 +774,7 @@ .id = 8, .dev = { .parent = &msm_device_iommu_rot.dev, + .platform_data = &rot_src_ctx, }, }; @@ -663,6 +783,7 @@ .id = 9, .dev = { .parent = &msm_device_iommu_rot.dev, + .platform_data = &rot_dst_ctx, }, }; @@ -671,6 +792,7 @@ .id = 10, .dev = { .parent = &msm_device_iommu_ijpeg.dev, + .platform_data = &ijpeg_src_ctx, }, }; @@ -679,6 +801,7 @@ .id = 11, .dev = { .parent = &msm_device_iommu_ijpeg.dev, + .platform_data = &ijpeg_dst_ctx, }, }; @@ -687,6 +810,7 @@ .id = 12, .dev = { .parent = &msm_device_iommu_vfe.dev, + .platform_data = &vfe_imgwr_ctx, }, }; @@ -695,6 +819,7 @@ .id = 13, .dev = { .parent = &msm_device_iommu_vfe.dev, + .platform_data = &vfe_misc_ctx, }, }; @@ -703,6 +828,7 @@ .id = 14, .dev = { .parent = &msm_device_iommu_vcodec_a.dev, + .platform_data = &vcodec_a_stream_ctx, }, }; @@ -711,6 +837,7 @@ .id = 15, .dev = { .parent = &msm_device_iommu_vcodec_a.dev, + .platform_data = &vcodec_a_mm1_ctx, }, }; @@ -719,6 +846,7 @@ .id = 16, .dev = { .parent = &msm_device_iommu_vcodec_b.dev, + .platform_data = &vcodec_b_mm2_ctx, }, }; @@ -727,6 +855,7 @@ .id = 17, .dev = { .parent = &msm_device_iommu_gfx3d.dev, + .platform_data = &gfx3d_user_ctx, }, }; @@ -735,6 +864,25 @@ .id = 18, .dev = { .parent = &msm_device_iommu_gfx3d.dev, + .platform_data = &gfx3d_priv_ctx, + }, +}; + +static struct platform_device msm_device_gfx3d1_user_ctx = { + .name = "msm_iommu_ctx", + .id = 19, + .dev = { + .parent = &msm_device_iommu_gfx3d1.dev, + .platform_data = &gfx3d1_user_ctx, + }, +}; + +static struct platform_device msm_device_gfx3d1_priv_ctx = { + .name = "msm_iommu_ctx", + .id = 20, + .dev = { + .parent = &msm_device_iommu_gfx3d1.dev, + .platform_data = &gfx3d1_priv_ctx, }, }; @@ -743,6 +891,7 @@ .id = 19, .dev = { .parent = &msm_device_iommu_gfx2d0.dev, + .platform_data = &gfx2d0_2d0_ctx, }, }; @@ -751,11 +900,29 @@ .id = 20, .dev = { .parent = &msm_device_iommu_gfx2d1.dev, + .platform_data = &gfx2d1_2d1_ctx, }, }; -static struct platform_device *msm_iommu_devs[] = { - &msm_device_iommu_jpegd, +static struct platform_device msm_device_vcap_vc_ctx = { + .name = "msm_iommu_ctx", + .id = 21, + .dev = { + .parent = &msm_device_iommu_vcap.dev, + .platform_data = &vcap_vc_ctx, + }, +}; + +static struct platform_device msm_device_vcap_vp_ctx = { + .name = "msm_iommu_ctx", + .id = 22, + .dev = { + .parent = &msm_device_iommu_vcap.dev, + .platform_data = &vcap_vp_ctx, + }, +}; + +static struct platform_device *msm_iommu_common_devs[] = { &msm_device_iommu_vpe, &msm_device_iommu_mdp0, &msm_device_iommu_mdp1, @@ -765,34 +932,32 @@ &msm_device_iommu_vcodec_a, &msm_device_iommu_vcodec_b, &msm_device_iommu_gfx3d, +}; + +static struct platform_device *msm_iommu_gfx2d_devs[] = { &msm_device_iommu_gfx2d0, &msm_device_iommu_gfx2d1, }; -static struct msm_iommu_dev *msm_iommu_data[] = { - &jpegd_iommu, - &vpe_iommu, - &mdp0_iommu, - &mdp1_iommu, - &rot_iommu, - &ijpeg_iommu, - &vfe_iommu, - &vcodec_a_iommu, - &vcodec_b_iommu, - &gfx3d_iommu, - &gfx2d0_iommu, - &gfx2d1_iommu, +static struct platform_device *msm_iommu_adreno3xx_gfx_devs[] = { + &msm_device_iommu_gfx3d1, }; -static struct platform_device *msm_iommu_ctx_devs[] = { - &msm_device_jpegd_src_ctx, - &msm_device_jpegd_dst_ctx, +static struct platform_device *msm_iommu_vcap_devs[] = { + &msm_device_iommu_vcap, +}; + +static struct platform_device *msm_iommu_jpegd_devs[] = { + &msm_device_iommu_jpegd, +}; + +static struct platform_device *msm_iommu_common_ctx_devs[] = { &msm_device_vpe_src_ctx, &msm_device_vpe_dst_ctx, - &msm_device_mdp_vg1_ctx, - &msm_device_mdp_rgb1_ctx, - &msm_device_mdp_vg2_ctx, - &msm_device_mdp_rgb2_ctx, + &msm_device_mdp_port0_cb0_ctx, + &msm_device_mdp_port0_cb1_ctx, + &msm_device_mdp_port1_cb0_ctx, + &msm_device_mdp_port1_cb1_ctx, &msm_device_rot_src_ctx, &msm_device_rot_dst_ctx, &msm_device_ijpeg_src_ctx, @@ -804,37 +969,35 @@ &msm_device_vcodec_b_mm2_ctx, &msm_device_gfx3d_user_ctx, &msm_device_gfx3d_priv_ctx, +}; + +static struct platform_device *msm_iommu_gfx2d_ctx_devs[] = { &msm_device_gfx2d0_2d0_ctx, &msm_device_gfx2d1_2d1_ctx, }; -static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { - &jpegd_src_ctx, - &jpegd_dst_ctx, - &vpe_src_ctx, - &vpe_dst_ctx, - &mdp_vg1_ctx, - &mdp_rgb1_ctx, - &mdp_vg2_ctx, - &mdp_rgb2_ctx, - &rot_src_ctx, - &rot_dst_ctx, - &ijpeg_src_ctx, - &ijpeg_dst_ctx, - &vfe_imgwr_ctx, - &vfe_misc_ctx, - &vcodec_a_stream_ctx, - &vcodec_a_mm1_ctx, - &vcodec_b_mm2_ctx, - &gfx3d_user_ctx, - &gfx3d_priv_ctx, - &gfx2d0_2d0_ctx, - &gfx2d1_2d1_ctx, +static struct platform_device *msm_iommu_adreno3xx_ctx_devs[] = { + &msm_device_gfx3d1_user_ctx, + &msm_device_gfx3d1_priv_ctx, +}; + +static struct platform_device *msm_iommu_vcap_ctx_devs[] = { + &msm_device_vcap_vc_ctx, + &msm_device_vcap_vp_ctx, }; -static int __init msm8x60_iommu_init(void) +static struct platform_device *msm_iommu_jpegd_ctx_devs[] = { + &msm_device_jpegd_src_ctx, + &msm_device_jpegd_dst_ctx, +}; + +static int __init iommu_init(void) { - int ret, i; + int ret; + if (!msm_soc_version_supports_iommu_v1()) { + pr_err("IOMMU v1 is not supported on this SoC version.\n"); + return -ENODEV; + } ret = platform_device_register(&msm_root_iommu_dev); if (ret != 0) { @@ -842,71 +1005,119 @@ goto failure; } - for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) { - ret = platform_device_add_data(msm_iommu_devs[i], - msm_iommu_data[i], - sizeof(struct msm_iommu_dev)); - if (ret != 0) { - pr_err("platform_device_add_data failed, " - "i = %d\n", i); - goto failure_unwind; - } - - ret = platform_device_register(msm_iommu_devs[i]); + /* Initialize common devs */ + platform_add_devices(msm_iommu_common_devs, + ARRAY_SIZE(msm_iommu_common_devs)); + + /* Initialize soc-specific devs */ + if (cpu_is_msm8x60() || cpu_is_msm8960()) { + platform_add_devices(msm_iommu_jpegd_devs, + ARRAY_SIZE(msm_iommu_jpegd_devs)); + platform_add_devices(msm_iommu_gfx2d_devs, + ARRAY_SIZE(msm_iommu_gfx2d_devs)); + } - if (ret != 0) { - pr_err("platform_device_register iommu failed, " - "i = %d\n", i); - goto failure_unwind; - } + if (soc_class_is_apq8064() || cpu_is_msm8960ab()) { + platform_add_devices(msm_iommu_jpegd_devs, + ARRAY_SIZE(msm_iommu_jpegd_devs)); + platform_add_devices(msm_iommu_adreno3xx_gfx_devs, + ARRAY_SIZE(msm_iommu_adreno3xx_gfx_devs)); + } + if (soc_class_is_apq8064()) + platform_add_devices(msm_iommu_vcap_devs, + ARRAY_SIZE(msm_iommu_vcap_devs)); + + /* Initialize common ctx_devs */ + ret = platform_add_devices(msm_iommu_common_ctx_devs, + ARRAY_SIZE(msm_iommu_common_ctx_devs)); + + /* Initialize soc-specific ctx_devs */ + if (cpu_is_msm8x60() || cpu_is_msm8960()) { + platform_add_devices(msm_iommu_jpegd_ctx_devs, + ARRAY_SIZE(msm_iommu_jpegd_ctx_devs)); + platform_add_devices(msm_iommu_gfx2d_ctx_devs, + ARRAY_SIZE(msm_iommu_gfx2d_ctx_devs)); } - for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) { - ret = platform_device_add_data(msm_iommu_ctx_devs[i], - msm_iommu_ctx_data[i], - sizeof(*msm_iommu_ctx_devs[i])); - if (ret != 0) { - pr_err("platform_device_add_data iommu failed, " - "i = %d\n", i); - goto failure_unwind2; - } + if (soc_class_is_apq8064() || cpu_is_msm8960ab()) { + platform_add_devices(msm_iommu_jpegd_ctx_devs, + ARRAY_SIZE(msm_iommu_jpegd_ctx_devs)); - ret = platform_device_register(msm_iommu_ctx_devs[i]); - if (ret != 0) { - pr_err("platform_device_register ctx failed, " - "i = %d\n", i); - goto failure_unwind2; - } + platform_add_devices(msm_iommu_adreno3xx_ctx_devs, + ARRAY_SIZE(msm_iommu_adreno3xx_ctx_devs)); } - return 0; + if (soc_class_is_apq8064()) + platform_add_devices(msm_iommu_vcap_ctx_devs, + ARRAY_SIZE(msm_iommu_vcap_ctx_devs)); -failure_unwind2: - while (--i >= 0) - platform_device_unregister(msm_iommu_ctx_devs[i]); -failure_unwind: - while (--i >= 0) - platform_device_unregister(msm_iommu_devs[i]); + return 0; - platform_device_unregister(&msm_root_iommu_dev); failure: return ret; } -static void __exit msm8x60_iommu_exit(void) +static void __exit iommu_exit(void) { int i; - for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) - platform_device_unregister(msm_iommu_ctx_devs[i]); + /* Common ctx_devs */ + for (i = 0; i < ARRAY_SIZE(msm_iommu_common_ctx_devs); i++) + platform_device_unregister(msm_iommu_common_ctx_devs[i]); + + /* Common devs. */ + for (i = 0; i < ARRAY_SIZE(msm_iommu_common_devs); ++i) + platform_device_unregister(msm_iommu_common_devs[i]); + + if (cpu_is_msm8x60() || cpu_is_msm8960()) { + for (i = 0; i < ARRAY_SIZE(msm_iommu_gfx2d_ctx_devs); i++) + platform_device_unregister(msm_iommu_gfx2d_ctx_devs[i]); + + for (i = 0; i < ARRAY_SIZE(msm_iommu_jpegd_ctx_devs); i++) + platform_device_unregister(msm_iommu_jpegd_ctx_devs[i]); - for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i) - platform_device_unregister(msm_iommu_devs[i]); + for (i = 0; i < ARRAY_SIZE(msm_iommu_gfx2d_devs); i++) + platform_device_unregister(msm_iommu_gfx2d_devs[i]); + + for (i = 0; i < ARRAY_SIZE(msm_iommu_jpegd_devs); i++) + platform_device_unregister(msm_iommu_jpegd_devs[i]); + } + if (soc_class_is_apq8064()) { + for (i = 0; i < ARRAY_SIZE(msm_iommu_vcap_ctx_devs); i++) + platform_device_unregister(msm_iommu_vcap_ctx_devs[i]); + } + + if (soc_class_is_apq8064() || cpu_is_msm8960ab()) { + for (i = 0; i < ARRAY_SIZE(msm_iommu_adreno3xx_ctx_devs); + i++) + platform_device_unregister( + msm_iommu_adreno3xx_ctx_devs[i]); + + for (i = 0; i < ARRAY_SIZE(msm_iommu_jpegd_ctx_devs); + i++) + platform_device_unregister( + msm_iommu_jpegd_ctx_devs[i]); + + if (soc_class_is_apq8064()) { + for (i = 0; i < ARRAY_SIZE(msm_iommu_vcap_devs); + i++) + platform_device_unregister( + msm_iommu_vcap_devs[i]); + } + + for (i = 0; i < ARRAY_SIZE(msm_iommu_adreno3xx_gfx_devs); + i++) + platform_device_unregister( + msm_iommu_adreno3xx_gfx_devs[i]); + + for (i = 0; i < ARRAY_SIZE(msm_iommu_jpegd_devs); i++) + platform_device_unregister(msm_iommu_jpegd_devs[i]); + } platform_device_unregister(&msm_root_iommu_dev); } -subsys_initcall(msm8x60_iommu_init); -module_exit(msm8x60_iommu_exit); +subsys_initcall(iommu_init); +module_exit(iommu_exit); MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Stepan Moskovchenko ");