--- zzzz-none-000/linux-3.10.107/arch/arm/mach-msm/devices-msm7x30.c 2017-06-27 09:49:32.000000000 +0000 +++ vr9-7490-729/linux-3.10.107/arch/arm/mach-msm/devices-msm7x30.c 2021-11-10 11:53:52.000000000 +0000 @@ -1,6 +1,6 @@ /* * Copyright (C) 2008 Google, Inc. - * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2012, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -15,55 +15,96 @@ #include #include - +#include #include -#include +#include +#include +#include +#include #include #include #include #include - +#include +#include #include "devices.h" -#include "smd_private.h" +#include "footswitch.h" #include -#include "clock-pcom.h" -#include "clock-7x30.h" +#include +#include +#include +#include +#include "pm.h" +#include "irq.h" -#include +struct platform_device msm7x30_device_acpuclk = { + .name = "acpuclk-7x30", + .id = -1, +}; -static struct resource msm_gpio_resources[] = { +/* EBI THERMAL DRIVER */ +static struct resource msm_ebi0_thermal_resources[] = { { - .start = 32 + 18, - .end = 32 + 18, - .flags = IORESOURCE_IRQ, - }, + .start = 0xA8600000, + .end = 0xA86005FF, + .name = "physbase", + .flags = IORESOURCE_MEM + } +}; + +struct platform_device msm_ebi0_thermal = { + .name = "msm_popmem-tm", + .id = 0, + .num_resources = 1, + .resource = msm_ebi0_thermal_resources +}; + +static struct resource msm_ebi1_thermal_resources[] = { { - .start = 32 + 19, - .end = 32 + 19, - .flags = IORESOURCE_IRQ, - }, + .start = 0xA8700000, + .end = 0xA87005FF, + .name = "physbase", + .flags = IORESOURCE_MEM + } +}; + +struct platform_device msm_ebi1_thermal = { + .name = "msm_popmem-tm", + .id = 1, + .num_resources = 1, + .resource = msm_ebi1_thermal_resources +}; + +static struct resource resources_adsp[] = { +{ + .start = INT_ADSP_A9_A11, + .end = INT_ADSP_A9_A11, + .flags = IORESOURCE_IRQ, +}, +}; + +struct platform_device msm_adsp_device = { + .name = "msm_adsp", + .id = -1, + .num_resources = ARRAY_SIZE(resources_adsp), + .resource = resources_adsp, +}; + +static struct resource resources_uart1[] = { { - .start = 0xac001000, - .end = 0xac001000 + SZ_4K - 1, - .flags = IORESOURCE_MEM, - .name = "gpio1" + .start = INT_UART1, + .end = INT_UART1, + .flags = IORESOURCE_IRQ, }, { - .start = 0xac101400, - .end = 0xac101400 + SZ_4K - 1, + .start = MSM7X30_UART1_PHYS, + .end = MSM7X30_UART1_PHYS + MSM7X30_UART1_SIZE - 1, .flags = IORESOURCE_MEM, - .name = "gpio2" }, }; -struct platform_device msm_device_gpio_7x30 = { - .name = "gpio-msm-7x30", - .num_resources = ARRAY_SIZE(msm_gpio_resources), - .resource = msm_gpio_resources, -}; - static struct resource resources_uart2[] = { { .start = INT_UART2, @@ -71,13 +112,33 @@ .flags = IORESOURCE_IRQ, }, { - .start = MSM_UART2_PHYS, - .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1, + .start = MSM7X30_UART2_PHYS, + .end = MSM7X30_UART2_PHYS + MSM7X30_UART2_SIZE - 1, .flags = IORESOURCE_MEM, .name = "uart_resource" }, }; +static struct resource resources_uart3[] = { + { + .start = INT_UART3, + .end = INT_UART3, + .flags = IORESOURCE_IRQ, + }, + { + .start = MSM7X30_UART3_PHYS, + .end = MSM7X30_UART3_PHYS + MSM7X30_UART3_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device msm_device_uart1 = { + .name = "msm_serial", + .id = 0, + .num_resources = ARRAY_SIZE(resources_uart1), + .resource = resources_uart1, +}; + struct platform_device msm_device_uart2 = { .name = "msm_serial", .id = 1, @@ -85,15 +146,194 @@ .resource = resources_uart2, }; -struct platform_device msm_device_smd = { - .name = "msm_smd", - .id = -1, +struct platform_device msm_device_uart3 = { + .name = "msm_serial", + .id = 2, + .num_resources = ARRAY_SIZE(resources_uart3), + .resource = resources_uart3, }; -static struct resource resources_otg[] = { +#define MSM_UART1DM_PHYS 0xA3300000 +#define MSM_UART2DM_PHYS 0xA3200000 +static struct resource msm_uart1_dm_resources[] = { + { + .start = MSM_UART1DM_PHYS, + .end = MSM_UART1DM_PHYS + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_UART1DM_IRQ, + .end = INT_UART1DM_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .start = INT_UART1DM_RX, + .end = INT_UART1DM_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = DMOV_HSUART1_TX_CHAN, + .end = DMOV_HSUART1_RX_CHAN, + .name = "uartdm_channels", + .flags = IORESOURCE_DMA, + }, + { + .start = DMOV_HSUART1_TX_CRCI, + .end = DMOV_HSUART1_RX_CRCI, + .name = "uartdm_crci", + .flags = IORESOURCE_DMA, + }, +}; + +static u64 msm_uart_dm1_dma_mask = DMA_BIT_MASK(32); + +struct platform_device msm_device_uart_dm1 = { + .name = "msm_serial_hs", + .id = 0, + .num_resources = ARRAY_SIZE(msm_uart1_dm_resources), + .resource = msm_uart1_dm_resources, + .dev = { + .dma_mask = &msm_uart_dm1_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource msm_uart2_dm_resources[] = { + { + .start = MSM_UART2DM_PHYS, + .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_UART2DM_IRQ, + .end = INT_UART2DM_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .start = INT_UART2DM_RX, + .end = INT_UART2DM_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = DMOV_HSUART2_TX_CHAN, + .end = DMOV_HSUART2_RX_CHAN, + .name = "uartdm_channels", + .flags = IORESOURCE_DMA, + }, + { + .start = DMOV_HSUART2_TX_CRCI, + .end = DMOV_HSUART2_RX_CRCI, + .name = "uartdm_crci", + .flags = IORESOURCE_DMA, + }, +}; + +static u64 msm_uart_dm2_dma_mask = DMA_BIT_MASK(32); + +struct platform_device msm_device_uart_dm2 = { + .name = "msm_serial_hs", + .id = 1, + .num_resources = ARRAY_SIZE(msm_uart2_dm_resources), + .resource = msm_uart2_dm_resources, + .dev = { + .dma_mask = &msm_uart_dm2_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +#define MSM_I2C_SIZE SZ_4K +#define MSM_I2C_PHYS 0xACD00000 +#define MSM_I2C_2_PHYS 0xACF00000 +static struct resource resources_i2c_2[] = { + { + .start = MSM_I2C_2_PHYS, + .end = MSM_I2C_2_PHYS + MSM_I2C_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_PWB_I2C_2, + .end = INT_PWB_I2C_2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_i2c_2 = { + .name = "msm_i2c", + .id = 2, + .num_resources = ARRAY_SIZE(resources_i2c_2), + .resource = resources_i2c_2, +}; + +static struct resource resources_i2c[] = { + { + .start = MSM_I2C_PHYS, + .end = MSM_I2C_PHYS + MSM_I2C_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_PWB_I2C, + .end = INT_PWB_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_i2c = { + .name = "msm_i2c", + .id = 0, + .num_resources = ARRAY_SIZE(resources_i2c), + .resource = resources_i2c, +}; + +#define MSM_QUP_PHYS 0xA8301000 +#define MSM_GSBI_QUP_I2C_PHYS 0xA8300000 +#define MSM_QUP_SIZE SZ_4K +static struct resource resources_qup[] = { + { + .name = "qup_phys_addr", + .start = MSM_QUP_PHYS, + .end = MSM_QUP_PHYS + MSM_QUP_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "gsbi_qup_i2c_addr", + .start = MSM_GSBI_QUP_I2C_PHYS, + .end = MSM_GSBI_QUP_I2C_PHYS + 4 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "qup_in_intr", + .start = INT_PWB_QUP_IN, + .end = INT_PWB_QUP_IN, + .flags = IORESOURCE_IRQ, + }, + { + .name = "qup_out_intr", + .start = INT_PWB_QUP_OUT, + .end = INT_PWB_QUP_OUT, + .flags = IORESOURCE_IRQ, + }, + { + .name = "qup_err_intr", + .start = INT_PWB_QUP_ERR, + .end = INT_PWB_QUP_ERR, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device qup_device_i2c = { + .name = "qup_i2c", + .id = 4, + .num_resources = ARRAY_SIZE(resources_qup), + .resource = resources_qup, +}; + + + +#define MSM_HSUSB_PHYS 0xA3600000 +static struct resource resources_hsusb_otg[] = { { .start = MSM_HSUSB_PHYS, - .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, + .end = MSM_HSUSB_PHYS + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { @@ -103,20 +343,35 @@ }, }; -struct platform_device msm_device_otg = { - .name = "msm_otg", +static u64 dma_mask = 0xffffffffULL; +struct platform_device msm_device_hsusb_otg = { + .name = "msm_hsusb_otg", .id = -1, - .num_resources = ARRAY_SIZE(resources_otg), - .resource = resources_otg, + .num_resources = ARRAY_SIZE(resources_hsusb_otg), + .resource = resources_hsusb_otg, .dev = { - .coherent_dma_mask = 0xffffffff, + .dma_mask = &dma_mask, + .coherent_dma_mask = 0xffffffffULL, + }, +}; + +static struct resource resources_hsusb_peripheral[] = { + { + .start = MSM_HSUSB_PHYS, + .end = MSM_HSUSB_PHYS + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_USB_HS, + .end = INT_USB_HS, + .flags = IORESOURCE_IRQ, }, }; -static struct resource resources_hsusb[] = { +static struct resource resources_gadget_peripheral[] = { { .start = MSM_HSUSB_PHYS, - .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, + .end = MSM_HSUSB_PHYS + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { @@ -126,21 +381,32 @@ }, }; -struct platform_device msm_device_hsusb = { +struct platform_device msm_device_hsusb_peripheral = { + .name = "msm_hsusb_peripheral", + .id = -1, + .num_resources = ARRAY_SIZE(resources_hsusb_peripheral), + .resource = resources_hsusb_peripheral, + .dev = { + .dma_mask = &dma_mask, + .coherent_dma_mask = 0xffffffffULL, + }, +}; + +struct platform_device msm_device_gadget_peripheral = { .name = "msm_hsusb", .id = -1, - .num_resources = ARRAY_SIZE(resources_hsusb), - .resource = resources_hsusb, + .num_resources = ARRAY_SIZE(resources_gadget_peripheral), + .resource = resources_gadget_peripheral, .dev = { - .coherent_dma_mask = 0xffffffff, + .dma_mask = &dma_mask, + .coherent_dma_mask = 0xffffffffULL, }, }; -static u64 dma_mask = 0xffffffffULL; static struct resource resources_hsusb_host[] = { { .start = MSM_HSUSB_PHYS, - .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, + .end = MSM_HSUSB_PHYS + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { @@ -152,90 +418,745 @@ struct platform_device msm_device_hsusb_host = { .name = "msm_hsusb_host", - .id = -1, + .id = 0, .num_resources = ARRAY_SIZE(resources_hsusb_host), .resource = resources_hsusb_host, .dev = { - .dma_mask = &dma_mask, - .coherent_dma_mask = 0xffffffffULL, + .dma_mask = &dma_mask, + .coherent_dma_mask = 0xffffffffULL, + }, +}; + +static struct platform_device *msm_host_devices[] = { + &msm_device_hsusb_host, +}; + +int msm_add_host(unsigned int host, struct msm_usb_host_platform_data *plat) +{ + struct platform_device *pdev; + + pdev = msm_host_devices[host]; + if (!pdev) + return -ENODEV; + pdev->dev.platform_data = plat; + return platform_device_register(pdev); +} + +struct platform_device asoc_msm_pcm = { + .name = "msm-dsp-audio", + .id = 0, +}; + +struct platform_device asoc_msm_dai0 = { + .name = "msm-codec-dai", + .id = 0, +}; + +struct platform_device asoc_msm_dai1 = { + .name = "msm-cpu-dai", + .id = 0, +}; + + +#define MSM_NAND_PHYS 0xA0200000 +#define MSM_NANDC01_PHYS 0xA0240000 +#define MSM_NANDC10_PHYS 0xA0280000 +#define MSM_NANDC11_PHYS 0xA02C0000 +#define EBI2_REG_BASE 0xA0000000 +static struct resource resources_nand[] = { + [0] = { + .name = "msm_nand_dmac", + .start = DMOV_NAND_CHAN, + .end = DMOV_NAND_CHAN, + .flags = IORESOURCE_DMA, + }, + [1] = { + .name = "msm_nand_phys", + .start = MSM_NAND_PHYS, + .end = MSM_NAND_PHYS + 0x7FF, + .flags = IORESOURCE_MEM, + }, + [2] = { + .name = "msm_nandc01_phys", + .start = MSM_NANDC01_PHYS, + .end = MSM_NANDC01_PHYS + 0x7FF, + .flags = IORESOURCE_MEM, + }, + [3] = { + .name = "msm_nandc10_phys", + .start = MSM_NANDC10_PHYS, + .end = MSM_NANDC10_PHYS + 0x7FF, + .flags = IORESOURCE_MEM, + }, + [4] = { + .name = "msm_nandc11_phys", + .start = MSM_NANDC11_PHYS, + .end = MSM_NANDC11_PHYS + 0x7FF, + .flags = IORESOURCE_MEM, + }, + [5] = { + .name = "ebi2_reg_base", + .start = EBI2_REG_BASE, + .end = EBI2_REG_BASE + 0x60, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource resources_otg[] = { + { + .start = MSM_HSUSB_PHYS, + .end = MSM_HSUSB_PHYS + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_USB_HS, + .end = INT_USB_HS, + .flags = IORESOURCE_IRQ, + }, + { + .name = "vbus_on", + .start = PMIC8058_IRQ_BASE + PM8058_CHGVAL_IRQ, + .end = PMIC8058_IRQ_BASE + PM8058_CHGVAL_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_otg = { + .name = "msm_otg", + .id = -1, + .num_resources = ARRAY_SIZE(resources_otg), + .resource = resources_otg, + .dev = { + .coherent_dma_mask = 0xffffffffULL, + }, +}; + +struct flash_platform_data msm_nand_data = { + .version = VERSION_2, +}; + +struct platform_device msm_device_nand = { + .name = "msm_nand", + .id = -1, + .num_resources = ARRAY_SIZE(resources_nand), + .resource = resources_nand, + .dev = { + .platform_data = &msm_nand_data, + }, +}; + +static struct msm_pm_irq_calls msm7x30_pm_irq_calls = { + .irq_pending = msm_irq_pending, + .idle_sleep_allowed = msm_irq_idle_sleep_allowed, + .enter_sleep1 = msm_irq_enter_sleep1, + .enter_sleep2 = msm_irq_enter_sleep2, + .exit_sleep1 = msm_irq_exit_sleep1, + .exit_sleep2 = msm_irq_exit_sleep2, + .exit_sleep3 = msm_irq_exit_sleep3, +}; + +void __init msm_pm_register_irqs(void) +{ + msm_pm_set_irq_extns(&msm7x30_pm_irq_calls); +} + +static struct resource smd_resource[] = { + { + .name = "a9_m2a_0", + .start = INT_A9_M2A_0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "a9_m2a_5", + .start = INT_A9_M2A_5, + .flags = IORESOURCE_IRQ, + }, + { + .name = "adsp_a11_smsm", + .start = INT_ADSP_A11, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smd_subsystem_config smd_config_list[] = { + { + .irq_config_id = SMD_MODEM, + .subsys_name = "modem", + .edge = SMD_APPS_MODEM, + + .smd_int.irq_name = "a9_m2a_0", + .smd_int.flags = IRQF_TRIGGER_RISING, + .smd_int.irq_id = -1, + .smd_int.device_name = "smd_dev", + .smd_int.dev_id = 0, + + .smd_int.out_bit_pos = 1 << 0, + .smd_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE, + .smd_int.out_offset = 0x8, + + .smsm_int.irq_name = "a9_m2a_5", + .smsm_int.flags = IRQF_TRIGGER_RISING, + .smsm_int.irq_id = -1, + .smsm_int.device_name = "smd_dev", + .smsm_int.dev_id = 0, + + .smsm_int.out_bit_pos = 1 << 5, + .smsm_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE, + .smsm_int.out_offset = 0x8, + + } +}; + +static struct smd_platform smd_platform_data = { + .num_ss_configs = ARRAY_SIZE(smd_config_list), + .smd_ss_configs = smd_config_list, +}; + +struct platform_device msm_device_smd = { + .name = "msm_smd", + .id = -1, + .resource = smd_resource, + .num_resources = ARRAY_SIZE(smd_resource), + .dev = { + .platform_data = &smd_platform_data, + } + +}; + +static struct resource msm_dmov_resource[] = { + { + .start = INT_ADM_AARM, + .flags = IORESOURCE_IRQ, + }, + { + .start = 0xAC400000, + .end = 0xAC400000 + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct msm_dmov_pdata msm_dmov_pdata = { + .sd = 2, + .sd_size = 0x400, +}; + +struct platform_device msm_device_dmov = { + .name = "msm_dmov", + .id = -1, + .resource = msm_dmov_resource, + .num_resources = ARRAY_SIZE(msm_dmov_resource), + .dev = { + .platform_data = &msm_dmov_pdata, + }, +}; + +#define MSM_SDC1_BASE 0xA0400000 +#define MSM_SDC2_BASE 0xA0500000 +#define MSM_SDC3_BASE 0xA3000000 +#define MSM_SDC4_BASE 0xA3100000 +static struct resource resources_sdc1[] = { + { + .name = "core_mem", + .start = MSM_SDC1_BASE, + .end = MSM_SDC1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "core_irq", + .start = INT_SDC1_0, + .end = INT_SDC1_1, + .flags = IORESOURCE_IRQ, + }, + { + .name = "dma_chnl", + .start = DMOV_SDC1_CHAN, + .end = DMOV_SDC1_CHAN, + .flags = IORESOURCE_DMA, + }, + { + .name = "dma_crci", + .start = DMOV_SDC1_CRCI, + .end = DMOV_SDC1_CRCI, + .flags = IORESOURCE_DMA, + } +}; + +static struct resource resources_sdc2[] = { + { + .name = "core_mem", + .start = MSM_SDC2_BASE, + .end = MSM_SDC2_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "core_irq", + .start = INT_SDC2_0, + .end = INT_SDC2_1, + .flags = IORESOURCE_IRQ, + }, + { + .name = "dma_chnl", + .start = DMOV_NAND_CHAN, + .end = DMOV_NAND_CHAN, + .flags = IORESOURCE_DMA, + }, + { + .name = "dma_crci", + .start = DMOV_SDC2_CRCI, + .end = DMOV_SDC2_CRCI, + .flags = IORESOURCE_DMA, + } +}; + +static struct resource resources_sdc3[] = { + { + .name = "core_mem", + .start = MSM_SDC3_BASE, + .end = MSM_SDC3_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "core_irq", + .start = INT_SDC3_0, + .end = INT_SDC3_1, + .flags = IORESOURCE_IRQ, + }, + { + .name = "dma_chnl", + .start = DMOV_SDC3_CHAN, + .end = DMOV_SDC3_CHAN, + .flags = IORESOURCE_DMA, + }, + { + .name = "dma_crci", + .start = DMOV_SDC3_CRCI, + .end = DMOV_SDC3_CRCI, + .flags = IORESOURCE_DMA, + }, +}; + +static struct resource resources_sdc4[] = { + { + .name = "core_mem", + .start = MSM_SDC4_BASE, + .end = MSM_SDC4_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "core_irq", + .start = INT_SDC4_0, + .end = INT_SDC4_1, + .flags = IORESOURCE_IRQ, + }, + { + .name = "dma_chnl", + .start = DMOV_SDC4_CHAN, + .end = DMOV_SDC4_CHAN, + .flags = IORESOURCE_DMA, + }, + { + .name = "dma_crci", + .start = DMOV_SDC4_CRCI, + .end = DMOV_SDC4_CRCI, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device msm_device_sdc1 = { + .name = "msm_sdcc", + .id = 1, + .num_resources = ARRAY_SIZE(resources_sdc1), + .resource = resources_sdc1, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device msm_device_sdc2 = { + .name = "msm_sdcc", + .id = 2, + .num_resources = ARRAY_SIZE(resources_sdc2), + .resource = resources_sdc2, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device msm_device_sdc3 = { + .name = "msm_sdcc", + .id = 3, + .num_resources = ARRAY_SIZE(resources_sdc3), + .resource = resources_sdc3, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device msm_device_sdc4 = { + .name = "msm_sdcc", + .id = 4, + .num_resources = ARRAY_SIZE(resources_sdc4), + .resource = resources_sdc4, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +static struct platform_device *msm_sdcc_devices[] __initdata = { + &msm_device_sdc1, + &msm_device_sdc2, + &msm_device_sdc3, + &msm_device_sdc4, +}; + +int __init msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat) +{ + struct platform_device *pdev; + + if (controller < 1 || controller > 4) + return -EINVAL; + + pdev = msm_sdcc_devices[controller-1]; + pdev->dev.platform_data = plat; + return platform_device_register(pdev); +} + +static struct resource msm_vidc_720p_resources[] = { + { + .start = 0xA3B00000, + .end = 0xA3B00000 + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_MFC720, + .end = INT_MFC720, + .flags = IORESOURCE_IRQ, + }, +}; + +#if defined(CONFIG_FB_MSM_MDP40) +#define MDP_BASE 0xA3F00000 +#define PMDH_BASE 0xAD600000 +#define EMDH_BASE 0xAD700000 +#define TVENC_BASE 0xAD400000 +#else +#define MDP_BASE 0xAA200000 +#define PMDH_BASE 0xAA600000 +#define EMDH_BASE 0xAA700000 +#define TVENC_BASE 0xAA400000 +#endif + +static struct resource msm_mdp_resources[] = { + { + .name = "mdp", + .start = MDP_BASE, + .end = MDP_BASE + 0x000F0000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_MDP, + .end = INT_MDP, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msm_mddi_resources[] = { + { + .name = "pmdh", + .start = PMDH_BASE, + .end = PMDH_BASE + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct resource msm_mddi_ext_resources[] = { + { + .name = "emdh", + .start = EMDH_BASE, + .end = EMDH_BASE + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct resource msm_ebi2_lcd_resources[] = { + { + .name = "base", + .start = 0xa0d00000, + .end = 0xa0d00000 + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "lcd01", + .start = 0x98000000, + .end = 0x98000000 + 0x80000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "lcd02", + .start = 0x9c000000, + .end = 0x9c000000 + 0x80000 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource msm_tvenc_resources[] = { + { + .name = "tvenc", + .start = TVENC_BASE, + .end = TVENC_BASE + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + + +static struct platform_device msm_mdp_device = { + .name = "mdp", + .id = 0, + .num_resources = ARRAY_SIZE(msm_mdp_resources), + .resource = msm_mdp_resources, +}; + +static struct platform_device msm_mddi_device = { + .name = "mddi", + .id = 0, + .num_resources = ARRAY_SIZE(msm_mddi_resources), + .resource = msm_mddi_resources, +}; + +static struct platform_device msm_mddi_ext_device = { + .name = "mddi_ext", + .id = 0, + .num_resources = ARRAY_SIZE(msm_mddi_ext_resources), + .resource = msm_mddi_ext_resources, +}; + +static struct platform_device msm_ebi2_lcd_device = { + .name = "ebi2_lcd", + .id = 0, + .num_resources = ARRAY_SIZE(msm_ebi2_lcd_resources), + .resource = msm_ebi2_lcd_resources, +}; + +static struct platform_device msm_lcdc_device = { + .name = "lcdc", + .id = 0, +}; + +static struct platform_device msm_dtv_device = { + .name = "dtv", + .id = 0, +}; + +static struct platform_device msm_tvenc_device = { + .name = "tvenc", + .id = 0, + .num_resources = ARRAY_SIZE(msm_tvenc_resources), + .resource = msm_tvenc_resources, +}; + + +/* TSIF begin */ +#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE) + +#define MSM_TSIF_PHYS (0xa3400000) +#define MSM_TSIF_SIZE (0x200) + +static struct resource tsif_resources[] = { + [0] = { + .flags = IORESOURCE_IRQ, + .start = INT_TSIF, + .end = INT_TSIF, + }, + [1] = { + .flags = IORESOURCE_MEM, + .start = MSM_TSIF_PHYS, + .end = MSM_TSIF_PHYS + MSM_TSIF_SIZE - 1, + }, + [2] = { + .flags = IORESOURCE_DMA, + .start = DMOV_TSIF_CHAN, + .end = DMOV_TSIF_CRCI, + }, +}; + +static void tsif_release(struct device *dev) +{ + dev_info(dev, "release\n"); +} + +struct platform_device msm_device_tsif = { + .name = "msm_tsif", + .id = 0, + .num_resources = ARRAY_SIZE(tsif_resources), + .resource = tsif_resources, + .dev = { + .release = tsif_release, + }, +}; +#endif /* defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE) */ +/* TSIF end */ + + + + +static void __init msm_register_device(struct platform_device *pdev, void *data) +{ + int ret; + + pdev->dev.platform_data = data; + + ret = platform_device_register(pdev); + if (ret) + dev_err(&pdev->dev, + "%s: platform_device_register() failed = %d\n", + __func__, ret); +} + +void __init msm_fb_register_device(char *name, void *data) +{ + if (!strncmp(name, "mdp", 3)) + msm_register_device(&msm_mdp_device, data); + else if (!strncmp(name, "pmdh", 4)) + msm_register_device(&msm_mddi_device, data); + else if (!strncmp(name, "emdh", 4)) + msm_register_device(&msm_mddi_ext_device, data); + else if (!strncmp(name, "ebi2", 4)) + msm_register_device(&msm_ebi2_lcd_device, data); + else if (!strncmp(name, "tvenc", 5)) + msm_register_device(&msm_tvenc_device, data); + else if (!strncmp(name, "lcdc", 4)) + msm_register_device(&msm_lcdc_device, data); + else if (!strncmp(name, "dtv", 3)) + msm_register_device(&msm_dtv_device, data); + else + printk(KERN_ERR "%s: unknown device! %s\n", __func__, name); +} + +struct resource kgsl_3d0_resources[] = { + { + .name = KGSL_3D0_REG_MEMORY, + .start = 0xA3500000, /* 3D GRP address */ + .end = 0xA351ffff, + .flags = IORESOURCE_MEM, + }, + { + .name = KGSL_3D0_IRQ, + .start = INT_GRP_3D, + .end = INT_GRP_3D, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct kgsl_device_platform_data kgsl_3d0_pdata = { + .pwrlevel = { + { + .gpu_freq = 245760000, + .bus_freq = 192000000, + }, + { + .gpu_freq = 192000000, + .bus_freq = 152000000, + }, + { + .gpu_freq = 192000000, + .bus_freq = 0, + }, + }, + .init_level = 0, + .num_levels = 3, + .set_grp_async = set_grp3d_async, + .idle_timeout = HZ/20, + .nap_allowed = true, + .idle_needed = true, + .clk_map = KGSL_CLK_SRC | KGSL_CLK_CORE | + KGSL_CLK_IFACE | KGSL_CLK_MEM, +}; + +struct platform_device msm_kgsl_3d0 = { + .name = "kgsl-3d0", + .id = 0, + .num_resources = ARRAY_SIZE(kgsl_3d0_resources), + .resource = kgsl_3d0_resources, + .dev = { + .platform_data = &kgsl_3d0_pdata, + }, +}; + +static struct resource kgsl_2d0_resources[] = { + { + .name = KGSL_2D0_REG_MEMORY, + .start = 0xA3900000, /* Z180 base address */ + .end = 0xA3900FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = KGSL_2D0_IRQ, + .start = INT_GRP_2D, + .end = INT_GRP_2D, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct kgsl_device_platform_data kgsl_2d0_pdata = { + .pwrlevel = { + { + .gpu_freq = 0, + .bus_freq = 192000000, + }, + }, + .init_level = 0, + .num_levels = 1, + /* HW workaround, run Z180 SYNC @ 192 MHZ */ + .set_grp_async = NULL, + .idle_timeout = HZ/10, + .nap_allowed = true, + .idle_needed = true, + .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE, +}; + +struct platform_device msm_kgsl_2d0 = { + .name = "kgsl-2d0", + .id = 0, + .num_resources = ARRAY_SIZE(kgsl_2d0_resources), + .resource = kgsl_2d0_resources, + .dev = { + .platform_data = &kgsl_2d0_pdata, + }, +}; + +struct platform_device *msm_footswitch_devices[] = { + FS_PCOM(FS_GFX2D0, "vdd", "kgsl-2d0.0"), + FS_PCOM(FS_GFX3D, "vdd", "kgsl-3d0.0"), + FS_PCOM(FS_MDP, "vdd", "mdp.0"), + FS_PCOM(FS_MFC, "fs_mfc", NULL), + FS_PCOM(FS_ROT, "vdd", "msm_rotator.0"), + FS_PCOM(FS_VFE, "fs_vfe", NULL), + FS_PCOM(FS_VPE, "fs_vpe", NULL), +}; +unsigned msm_num_footswitch_devices = ARRAY_SIZE(msm_footswitch_devices); + +static struct resource gpio_resources[] = { + { + .start = INT_GPIO_GROUP1, + .flags = IORESOURCE_IRQ, + }, + { + .start = INT_GPIO_GROUP2, + .flags = IORESOURCE_IRQ, }, }; -struct clk_lookup msm_clocks_7x30[] = { - CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), - CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), - CLK_PCOM("cam_m_clk", CAM_M_CLK, NULL, 0), - CLK_PCOM("camif_pad_pclk", CAMIF_PAD_P_CLK, NULL, OFF), - CLK_PCOM("ce_clk", CE_CLK, NULL, 0), - CLK_PCOM("codec_ssbi_clk", CODEC_SSBI_CLK, NULL, 0), - CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), - CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0), - CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX), - CLK_PCOM("emdh_pclk", EMDH_P_CLK, NULL, OFF), - CLK_PCOM("gp_clk", GP_CLK, NULL, 0), - CLK_PCOM("grp_2d_clk", GRP_2D_CLK, NULL, 0), - CLK_PCOM("grp_2d_pclk", GRP_2D_P_CLK, NULL, 0), - CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0), - CLK_PCOM("grp_pclk", GRP_3D_P_CLK, NULL, 0), - CLK_7X30S("grp_src_clk", GRP_3D_SRC_CLK, GRP_3D_CLK, NULL, 0), - CLK_PCOM("hdmi_clk", HDMI_CLK, NULL, 0), - CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF), - CLK_PCOM("jpeg_clk", JPEG_CLK, NULL, OFF), - CLK_PCOM("jpeg_pclk", JPEG_P_CLK, NULL, OFF), - CLK_PCOM("lpa_codec_clk", LPA_CODEC_CLK, NULL, 0), - CLK_PCOM("lpa_core_clk", LPA_CORE_CLK, NULL, 0), - CLK_PCOM("lpa_pclk", LPA_P_CLK, NULL, 0), - CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0), - CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX), - CLK_PCOM("mddi_pclk", PMDH_P_CLK, NULL, 0), - CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF), - CLK_PCOM("mdp_pclk", MDP_P_CLK, NULL, 0), - CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0), - CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0), - CLK_PCOM("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, 0), - CLK_PCOM("mfc_clk", MFC_CLK, NULL, 0), - CLK_PCOM("mfc_div2_clk", MFC_DIV2_CLK, NULL, 0), - CLK_PCOM("mfc_pclk", MFC_P_CLK, NULL, 0), - CLK_PCOM("mi2s_m_clk", MI2S_M_CLK, NULL, 0), - CLK_PCOM("mi2s_s_clk", MI2S_S_CLK, NULL, 0), - CLK_PCOM("mi2s_codec_rx_m_clk", MI2S_CODEC_RX_M_CLK, NULL, 0), - CLK_PCOM("mi2s_codec_rx_s_clk", MI2S_CODEC_RX_S_CLK, NULL, 0), - CLK_PCOM("mi2s_codec_tx_m_clk", MI2S_CODEC_TX_M_CLK, NULL, 0), - CLK_PCOM("mi2s_codec_tx_s_clk", MI2S_CODEC_TX_S_CLK, NULL, 0), - CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN), - CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), - CLK_PCOM("rotator_clk", AXI_ROTATOR_CLK, NULL, 0), - CLK_PCOM("rotator_imem_clk", ROTATOR_IMEM_CLK, NULL, OFF), - CLK_PCOM("rotator_pclk", ROTATOR_P_CLK, NULL, OFF), - CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), - CLK_PCOM("spi_clk", SPI_CLK, NULL, 0), - CLK_PCOM("spi_pclk", SPI_P_CLK, NULL, 0), - CLK_7X30S("tv_src_clk", TV_CLK, TV_ENC_CLK, NULL, 0), - CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), - CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), - CLK_PCOM("uart_clk", UART2_CLK, "msm_serial.1", 0), - CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0), - CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), - CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF), - CLK_PCOM("usb_hs_core_clk", USB_HS_CORE_CLK, NULL, OFF), - CLK_PCOM("usb_hs2_clk", USB_HS2_CLK, NULL, OFF), - CLK_PCOM("usb_hs2_pclk", USB_HS2_P_CLK, NULL, OFF), - CLK_PCOM("usb_hs2_core_clk", USB_HS2_CORE_CLK, NULL, OFF), - CLK_PCOM("usb_hs3_clk", USB_HS3_CLK, NULL, OFF), - CLK_PCOM("usb_hs3_pclk", USB_HS3_P_CLK, NULL, OFF), - CLK_PCOM("usb_hs3_core_clk", USB_HS3_CORE_CLK, NULL, OFF), - CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF | CLK_MIN), - CLK_PCOM("vfe_camif_clk", VFE_CAMIF_CLK, NULL, 0), - CLK_PCOM("vfe_clk", VFE_CLK, NULL, 0), - CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, 0), - CLK_PCOM("vfe_pclk", VFE_P_CLK, NULL, OFF), - CLK_PCOM("vpe_clk", VPE_CLK, NULL, 0), - - /* 7x30 v2 hardware only. */ - CLK_PCOM("csi_clk", CSI0_CLK, NULL, 0), - CLK_PCOM("csi_pclk", CSI0_P_CLK, NULL, 0), - CLK_PCOM("csi_vfe_clk", CSI0_VFE_CLK, NULL, 0), +static struct platform_device msm_device_gpio = { + .name = "msmgpio", + .id = -1, + .resource = gpio_resources, + .num_resources = ARRAY_SIZE(gpio_resources), }; -unsigned msm_num_clocks_7x30 = ARRAY_SIZE(msm_clocks_7x30); +static int __init msm7630_init_gpio(void) +{ + platform_device_register(&msm_device_gpio); + return 0; +} +postcore_initcall(msm7630_init_gpio);