--- zzzz-none-000/linux-3.10.107/arch/mips/Kconfig 2017-06-27 09:49:32.000000000 +0000 +++ vr9-7490-729/linux-3.10.107/arch/mips/Kconfig 2021-11-10 11:53:53.000000000 +0000 @@ -7,6 +7,8 @@ select HAVE_PERF_EVENTS select PERF_USE_VMALLOC select HAVE_ARCH_KGDB + select HAVE_ARCH_SECCOMP_FILTER + select HAVE_ARCH_TRACEHOOK select ARCH_HAVE_CUSTOM_GPIO_H select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_TRACE_MCOUNT_TEST @@ -90,18 +92,17 @@ config ATH79 bool "Atheros AR71XX/AR724X/AR913X based boards" - select ARCH_REQUIRE_GPIOLIB select BOOT_RAW select CEVT_R4K select CSRC_R4K select DMA_NONCOHERENT select HAVE_CLK select IRQ_CPU - select MIPS_MACHINE select SYS_HAS_CPU_MIPS32_R2 select SYS_HAS_EARLY_PRINTK select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN + select USE_OF help Support for the Atheros AR71XX/AR724X/AR913X SoCs. @@ -115,6 +116,7 @@ select FW_CFE select HW_HAS_PCI select IRQ_CPU + select SYS_HAS_CPU_MIPS32_R1 select NO_EXCEPT_FILL select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN @@ -157,6 +159,25 @@ select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN +config MACH_FUSIV + bool "Fusiv processor based boards" + select SYS_HAS_EARLY_PRINTK + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_32BIT_KERNEL + select BOOT_ELF32 + select DMA_NONCOHERENT + select IRQ_CPU + select HW_HAS_PCI + select CPU_HAS_LLSC + select CPU_MIPSR2_IRQ_VI + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select CEVT_R4K + select CSRC_R4K + select USE_OF + config MACH_DECSTATION bool "DECstations" select BOOT_ELF32 @@ -251,6 +272,7 @@ select USE_OF select PINCTRL select PINCTRL_LANTIQ + select NR_CPUS_DEFAULT_2 config LASAT bool "LASAT Networks platforms" @@ -312,6 +334,7 @@ select SWAP_IO_SPACE select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_CPU_MIPS32_R2_EVA select SYS_HAS_CPU_MIPS64_R1 select SYS_HAS_CPU_MIPS64_R2 select SYS_HAS_CPU_NEVADA @@ -322,9 +345,11 @@ select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_MIPS_CMP + select SYS_SUPPORTS_MIPS_CPS select SYS_SUPPORTS_MULTITHREADING select SYS_SUPPORTS_SMARTMIPS select SYS_SUPPORTS_ZBOOT + select SYS_SUPPORTS_HIGHMEM help This enables support for the MIPS Technologies Malta evaluation board. @@ -341,7 +366,6 @@ select DMA_NONCOHERENT select IRQ_CPU select IRQ_GIC - select MIPS_CPU_SCACHE select MIPS_MSC select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 @@ -420,7 +444,6 @@ select CSRC_POWERTV select DMA_NONCOHERENT select HW_HAS_PCI - select SYS_HAS_EARLY_PRINTK select SYS_HAS_CPU_MIPS32_R2 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN @@ -608,7 +631,6 @@ select BOOT_ELF32 select DMA_COHERENT select HAVE_PATA_PLATFORM - select NR_CPUS_DEFAULT_2 select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 @@ -622,7 +644,6 @@ select BOOT_ELF32 select DMA_COHERENT select HAVE_PATA_PLATFORM - select NR_CPUS_DEFAULT_2 select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 @@ -634,7 +655,6 @@ bool "Sibyte BCM91250E-Sentosa" select BOOT_ELF32 select DMA_COHERENT - select NR_CPUS_DEFAULT_2 select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 @@ -838,6 +858,7 @@ endchoice +source "arch/mips/fusiv/Kconfig" source "arch/mips/alchemy/Kconfig" source "arch/mips/ath79/Kconfig" source "arch/mips/bcm47xx/Kconfig" @@ -980,6 +1001,17 @@ config MIPS_BONITO64 bool +config MIPS_FPU_EMU + bool "Enable FPU emulation" + default y + help + This option allows building a kernel with or without the Algorithmics + FPU emulator enabled. Turning off this option results in a kernel which + does not catch floating operations exceptions. Make sure that your toolchain + is configured to enable software floating point emulation in that case. + + If unsure say Y here. + config MIPS_MSC bool @@ -1010,6 +1042,13 @@ config HOLES_IN_ZONE bool +config CPU_HAS_DSP_ASE + bool "MIPS DSP Extension" + default n + help + Enable this option for the mips dsp application specific extension + support in the cpu + # # Endianness selection. Sufficiently obscure so many users don't know what to # answer,so we try hard to limit the available choices. Also the use of a @@ -1242,6 +1281,36 @@ specific type of processor in your system, choose those that one otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system. +config CPU_MIPS_24K + bool "MIPS24Kc" + depends on SYS_HAS_CPU_MIPS32_R2 + select CPU_HAS_PREFETCH + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + help + Choose this option to build a kernel for release 2 or later of the + MIPS32 architecture. Special Version 24kc + +config CPU_MIPS_34K + bool "MIPS34Kc" + depends on SYS_HAS_CPU_MIPS32_R2 + select CPU_HAS_PREFETCH + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + help + Choose this option to build a kernel for release 2 or later of the + MIPS32 architecture. Special Version 34kc + +config CPU_MIPS_74K + bool "MIPS74Kc" + depends on SYS_HAS_CPU_MIPS32_R2 + select CPU_HAS_PREFETCH + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + help + Choose this option to build a kernel for release 2 or later of the + MIPS32 architecture. Special Version 74kc + config CPU_MIPS64_R1 bool "MIPS64 Release 1" depends on SYS_HAS_CPU_MIPS64_R1 @@ -1495,6 +1564,47 @@ Netlogic Microsystems XLP processors. endchoice +config CPU_MIPS32_R2_EVA + bool "MIPS32 Release 2 with EVA support" + depends on SYS_HAS_CPU_MIPS32_R2_EVA + depends on CPU_MIPS32_R2 + select EVA + help + Choose this option to build a kernel for release 2 or later of the + MIPS32 architecture working in EVA mode. EVA is an Extended Virtual + Addressing but it actually allows extended direct physical memory + addressing in kernel (more than 512MB - 2GB or 3GB). If you know the + specific type of processor in your system, choose those that one + otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system. + If unsure, select just CPU_MIPS32_R2 or even CPU_MIPS32_R1. + +config EVA_OLD_MALTA_MAP + bool "Old memory map on Malta (sys controller 1.418)" + depends on EVA + help + Choose this option to build EVA kernel for old Malta memory map. + All memory are located above 0x80000000 and first 256M is mirrored + to first 0x80000000. IOCU doesn't work with this option. + It is designed for systems with RocIt system controller 1.418/1.424 + and it is kept just for MTI testing purposes. (1.424 can be used + with new memory map too). + May or may not work with SMP - address aliasing is crazy for YAMON. + +config EVA_3GB + bool "EVA support for 3GB memory" + depends on EVA + depends on EVA_OLD_MALTA_MAP + help + Choose this option to build a EVA kernel supporting up to 3GB of + physical memory. This option shifts uncacheble IO registers from KSEG1 + to KSEG3 which becomes uncachable and KSEG1 (+KSEG0) can be used for + additional 1GB physical memory. Actually, to minimize changes in + drivers and code the same name (KSEG1) will still be used but it's + address will be changed. The physical I/O address is still the same. + On Malta board with old memory map it doesn't give you 3GB + (because of PCI bridges loop) but it can be used as a start point + for development. + if CPU_LOONGSON2F config CPU_NOP_WORKAROUNDS bool @@ -1575,6 +1685,9 @@ config SYS_HAS_CPU_MIPS32_R2 bool +config SYS_HAS_CPU_MIPS32_R2_EVA + bool + config SYS_HAS_CPU_MIPS64_R1 bool @@ -1667,7 +1780,7 @@ # config CPU_MIPS32 bool - default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 + default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS_24K || CPU_MIPS_34K || CPU_MIPS_74K config CPU_MIPS64 bool @@ -1682,7 +1795,10 @@ config CPU_MIPSR2 bool - default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON + default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON || CPU_MIPS_24K || CPU_MIPS_34K || CPU_MIPS_74K + +config EVA + bool config SYS_SUPPORTS_32BIT_KERNEL bool @@ -1737,6 +1853,7 @@ config KVM_GUEST bool "KVM Guest Kernel" + depends on BROKEN_ON_SMP help Select this option if building a guest kernel for KVM (Trap & Emulate) mode @@ -1878,67 +1995,77 @@ bool default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON) +source "drivers/cpuidle/Kconfig" + choice prompt "MIPS MT options" config MIPS_MT_DISABLED - bool "Disable multithreading support." + bool "Disable multithreading support" + depends on !FUSIV_SMP help - Use this option if your workload can't take advantage of - MIPS hardware multithreading support. On systems that don't have - the option of an MT-enabled processor this option will be the only - option in this menu. + Use this option if your platform does not support the MT ASE + which is hardware multithreading support. On systems without + an MT-enabled processor, this will be the only option that is + available in this menu. config MIPS_MT_SMP bool "Use 1 TC on each available VPE for SMP" depends on SYS_SUPPORTS_MULTITHREADING + depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON || CPU_MIPS_24K || CPU_MIPS_34K || CPU_MIPS_74K select CPU_MIPSR2_IRQ_VI - select CPU_MIPSR2_IRQ_EI + select CPU_MIPSR2_IRQ_EI if !(FUSIV_VX585 || FUSIV_VX185) select MIPS_MT - select NR_CPUS_DEFAULT_2 select SMP - select SYS_SUPPORTS_SCHED_SMT if SMP - select SYS_SUPPORTS_SMP select SMP_UP + select SYS_SUPPORTS_SMP + select SYS_SUPPORTS_SCHED_SMT select MIPS_PERF_SHARED_TC_COUNTERS help - This is a kernel model which is known a VSMP but lately has been - marketesed into SMVP. - Virtual SMP uses the processor's VPEs to implement virtual - processors. In currently available configuration of the 34K processor - this allows for a dual processor. Both processors will share the same - primary caches; each will obtain the half of the TLB for it's own - exclusive use. For a layman this model can be described as similar to - what Intel calls Hyperthreading. - - For further information see http://www.linux-mips.org/wiki/34K#VSMP + This is a kernel model which is known as SMVP. This is supported + on cores with the MT ASE and uses the available VPEs to implement + virtual processors which supports SMP. This is equivalent to the + Intel Hyperthreading feature. For further information go to + . config MIPS_MT_SMTC - bool "SMTC: Use all TCs on all VPEs for SMP" - depends on CPU_MIPS32_R2 - #depends on CPU_MIPS64_R2 # once there is hardware ... + bool "Use all TCs on all VPEs for SMP (DEPRECATED)" + depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON || CPU_MIPS_24K || CPU_MIPS_34K || CPU_MIPS_74K depends on SYS_SUPPORTS_MULTITHREADING + depends on !MIPS_CPS select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select MIPS_MT - select NR_CPUS_DEFAULT_8 select SMP - select SYS_SUPPORTS_SMP select SMP_UP + select SYS_SUPPORTS_SMP + select SYS_SUPPORTS_SCHED_SMT + select NR_CPUS_DEFAULT_8 help - This is a kernel model which is known a SMTC or lately has been - marketesed into SMVP. - is presenting the available TC's of the core as processors to Linux. - On currently available 34K processors this means a Linux system will - see up to 5 processors. The implementation of the SMTC kernel differs - significantly from VSMP and cannot efficiently coexist in the same - kernel binary so the choice between VSMP and SMTC is a compile time - decision. - - For further information see http://www.linux-mips.org/wiki/34K#SMTC + This is a kernel model which is known as SMTC. This is + supported on cores with the MT ASE and presents all TCs + available on all VPEs to support SMP. For further + information see . endchoice +config MIPS_MT_SMTC_IPI_DEBUG + bool "Add SMTC debug informations into (struct smtc_ipi)" + depends on MIPS_MT_SMTC + help + This option adds pointers to ipi sender and timestamp, possibly + allowing better debugging. + +config MIPS_MT_TC_LIMIT + int "SMTC: Limit usable TCs" + depends on MIPS_MT_SMTC + default 0 + range 0 64 + help + This option sets the default value for the kernel command line option + "maxtcs". Per default there is no limit (0), thus all thread + contexts will be used. + config MIPS_MT bool @@ -1962,9 +2089,19 @@ default y depends on MIPS_MT_SMP || MIPS_MT_SMTC +config MIPS_INCOMPATIBLE_FPU_EMULATION + bool "Emulation of incompatible FPU" + default n + depends on !CPU_MIPS32_R2 && !CPU_MIPS64_R1 && !CPU_MIPS64_R2 + help + Emulation of 32x32bit or 32x64bit FPU ELFs on incompatible FPU. + CP0_Status.FR bit controls switch between both models but + some CPU may not have this capability. + If unsure, leave N here. + config MIPS_VPE_LOADER bool "VPE loader support." - depends on SYS_SUPPORTS_MULTITHREADING + depends on SYS_SUPPORTS_MULTITHREADING && MODULES select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select MIPS_MT @@ -1972,6 +2109,51 @@ Includes a loader for loading an elf relocatable object onto another VPE and running it. +config IFX_VPE_EXT + bool "IFX APRP Extensions" + depends on MIPS_VPE_LOADER + default y + help + IFX included extensions in APRP + +config IFX_VPE_CACHE_SPLIT + bool "IFX Cache Split Ways" + depends on IFX_VPE_EXT + help + IFX extension for reserving (splitting) cache ways among VPEs. You must + give kernel command line arguments vpe_icache_shared=0 or + vpe_dcache_shared=0 to enable splitting of icache or dcache + respectively. Then you can specify which cache ways should be + assigned to which VPE. There are total 8 cache ways, 4 each + for dcache and icache: dcache_way0, dcache_way1,dcache_way2, + dcache_way3 and icache_way0,icache_way1, icache_way2,icache_way3. + + For example, if you specify vpe_icache_shared=0 and icache_way2=1, + then the 3rd icache way will be assigned to VPE0 and denied in VPE1. + + For icache, software is required to make atleast one cache way available + for a VPE at all times i.e., one can't assign all the icache ways to one VPE. + + By default, vpe_dcache_shared and vpe_icache_shared are set to 1 + (i.e., both icache and dcache are shared among VPEs) + +source "arch/mips/avm_enh/Kconfig" + +config PERFCTRS + bool "34K Performance counters" + depends on MIPS_MT && PROC_FS + default n + help + 34K Performance counter through /proc + +config MTSCHED + bool "Support mtsched priority configuration for TCs" + depends on MIPS_MT && PROC_FS + default y + help + Support for mtsched priority configuration for TCs through + /proc/mips/mtsched + config MIPS_MT_SMTC_IM_BACKSTOP bool "Use per-TC register bits as backstop for inhibited IM bits" depends on MIPS_MT_SMTC @@ -2013,15 +2195,43 @@ config MIPS_CMP bool "MIPS CMP framework support" - depends on SYS_SUPPORTS_MIPS_CMP - select SYNC_R4K - select SYS_SUPPORTS_SMP - select SYS_SUPPORTS_SCHED_SMT if SMP + depends on SYS_SUPPORTS_MIPS_CMP && !MIPS_MT_SMTC + select MIPS_GIC_IPI + select SYNC_R4K if !(FUSIV_VX585 && FUSIV_SMP) select WEAK_ORDERING default n help - This is a placeholder option for the GCMP work. It will need to - be handled differently... + Select this if you are using a bootloader which implements the "CMP + framework" protocol (ie. YAMON) and want your kernel to make use of + its ability to start secondary CPUs. + +config MIPS_CPS + bool "MIPS Coherent Processing System support" + depends on SYS_SUPPORTS_MIPS_CPS + select MIPS_CPC + select MIPS_GIC_IPI + select SMP + select SYNC_R4K if ((CEVT_R4K || CSRC_R4K) && !(FUSIV_VX585 && FUSIV_SMP)) + select SYS_SUPPORTS_SMP + select WEAK_ORDERING + help + Select this if you wish to run an SMP kernel across multiple cores + within a MIPS Coherent Processing System. When this option is + enabled the kernel will probe for other cores and boot them with + no external assistance. It is safe to enable this when hardware + support is unavailable. + +config MIPS_CPC + bool + +config MIPS_GIC_IPI + bool + +config MIPS_CPUIDLE_CPS + bool + depends on CPU_MIPSR2 && !MIPS_MT_SMTC + default y if CPU_IDLE && MIPS_CMP + select ARCH_NEEDS_CPU_IDLE_COUPLED if MIPS_MT config SB1_PASS_1_WORKAROUNDS bool @@ -2116,6 +2326,8 @@ config HIGHMEM bool "High Memory Support" depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM + depends on ( !SMP || NR_CPUS = 1 || NR_CPUS = 2 || NR_CPUS = 3 || NR_CPUS = 4 || NR_CPUS = 5 || NR_CPUS = 6 || NR_CPUS = 7 || NR_CPUS = 8 ) + depends on !CPU_MIPS32_R2_EVA config CPU_SUPPORTS_HIGHMEM bool @@ -2203,10 +2415,10 @@ config SYS_SUPPORTS_MIPS_CMP bool -config SYS_SUPPORTS_SMP +config SYS_SUPPORTS_MIPS_CPS bool -config NR_CPUS_DEFAULT_1 +config SYS_SUPPORTS_SMP bool config NR_CPUS_DEFAULT_2 @@ -2229,9 +2441,8 @@ config NR_CPUS int "Maximum number of CPUs (2-64)" - range 1 64 if NR_CPUS_DEFAULT_1 + range 2 64 depends on SMP - default "1" if NR_CPUS_DEFAULT_1 default "2" if NR_CPUS_DEFAULT_2 default "4" if NR_CPUS_DEFAULT_4 default "8" if NR_CPUS_DEFAULT_8 @@ -2409,11 +2620,22 @@ config HW_HAS_PCI bool +config ATH_HAS_PCI_RC2 + bool "Support for PCI controller RC2" + depends on HW_HAS_PCI + select PCI_DOMAINS + help + Find out whether you have a RC2 in the system. RC2 is the name of a + 2nd PCIe Root Complex.Other default Root Complex is RC1. + If you have RC2,say Y, otherwise N. + + config PCI bool "Support for PCI controller" depends on HW_HAS_PCI select PCI_DOMAINS select NO_GENERIC_PCI_IOPORT_MAP + select ARCH_SUPPORTS_MSI if ((VR9 || AR10) && IFX_PCIE) help Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff inside @@ -2427,6 +2649,11 @@ source "drivers/pci/pcie/Kconfig" +config ATH_LOW_POWER_ENABLE + bool "Enable Low-Power-Support for Atheros PCIe" + depends on MACH_934x + default n + # # ISA support is now enabled via select. Too many systems still have the one # or other ISA chip on the board that users don't know about so don't expect @@ -2507,6 +2734,7 @@ config MIPS32_COMPAT bool "Kernel support for Linux/MIPS 32-bit binary compatibility" depends on 64BIT + default y if CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL help Select this option if you want Linux/MIPS 32-bit binary compatibility. Since all software available for Linux/MIPS is @@ -2526,6 +2754,7 @@ config MIPS32_O32 bool "Kernel support for o32 binaries" depends on MIPS32_COMPAT + default y if CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL help Select this option if you want to run o32 binaries. These are pure 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of @@ -2544,6 +2773,10 @@ If unsure, say N. +comment "64bit kernel, but support of 32bit applications is disabled!" + depends on 64BIT && !MIPS32_O32 && !MIPS32_N32 + depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL + config BINFMT_ELF32 bool default y if MIPS32_O32 || MIPS32_N32 @@ -2557,7 +2790,7 @@ depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP config ARCH_SUSPEND_POSSIBLE - def_bool y + def_bool n depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP source "kernel/power/Kconfig" @@ -2567,12 +2800,41 @@ config MIPS_EXTERNAL_TIMER bool -if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER +if CPU_SUPPORTS_CPUFREQ menu "CPU Power Management" source "drivers/cpufreq/Kconfig" +source "drivers/cpuidle/Kconfig" + +config AVM_CPUFREQ + bool "AVM CPUFREQ interface support" + depends on PM && (LANTIQ || MIPS_UR8) + default no + help + This option will enable CPUFREQ interface support on LANTIQ/UR8 + +config AVM_CPUIDLE + bool "AVM CPUIDLE interface support" + depends on PM && (LANTIQ || MIPS_UR8) + default no + help + This option will enable CPUIDLE interface support on LANTIQ/UR8 endmenu endif +config AVM_IPI_YIELD + bool "AVM IPI extended Yield interface support" + depends on SMP && VR9 + default no + help + This option will enable extended usage of yield-thread-context + +config AVM_IPI_YIELD_DEBUG + bool "AVM IPI extended Yield interface support" + depends on AVM_IPI_YIELD + default no + help + This option will enable extended usage of yield-thread-context + source "net/Kconfig" source "drivers/Kconfig" @@ -2590,3 +2852,4 @@ source "lib/Kconfig" source "arch/mips/kvm/Kconfig" +