--- zzzz-none-000/linux-3.10.107/arch/mips/ath79/dev-common.c	2017-06-27 09:49:32.000000000 +0000
+++ vr9-7490-729/linux-3.10.107/arch/mips/ath79/dev-common.c	2021-11-10 11:53:53.000000000 +0000
@@ -18,16 +18,17 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 
+#include <asm/time.h>		/* for mips_hpt_frequency */
 #include <asm/mach-ath79/ath79.h>
-#include <asm/mach-ath79/ar71xx_regs.h>
+#include <atheros.h>
 #include <asm/mach-ath79/ar933x_uart_platform.h>
 #include "common.h"
 #include "dev-common.h"
 
 static struct resource ath79_uart_resources[] = {
 	{
-		.start	= AR71XX_UART_BASE,
-		.end	= AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
+		.start	= ATH_UART_BASE,
+		.end	= ATH_UART_BASE + ATH_UART_SIZE - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
@@ -35,7 +36,7 @@
 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
 static struct plat_serial8250_port ath79_uart_data[] = {
 	{
-		.mapbase	= AR71XX_UART_BASE,
+		.mapbase	= ATH_UART_BASE,
 		.irq		= ATH79_MISC_IRQ(3),
 		.flags		= AR71XX_UART_FLAGS,
 		.iotype		= UPIO_MEM32,
@@ -55,6 +56,7 @@
 	},
 };
 
+#if (defined CONFIG_SOC_AR933X)
 static struct resource ar933x_uart_resources[] = {
 	{
 		.start	= AR933X_UART_BASE,
@@ -78,28 +80,38 @@
 		.platform_data	= &ar933x_uart_data,
 	},
 };
+#endif
 
 void __init ath79_register_uart(void)
 {
 	struct clk *clk;
 
 	clk = clk_get(NULL, "uart");
-	if (IS_ERR(clk))
+	if (IS_ERR(clk)) {
 		panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
+    }
 
 	if (soc_is_ar71xx() ||
 	    soc_is_ar724x() ||
 	    soc_is_ar913x() ||
 	    soc_is_ar934x() ||
-	    soc_is_qca955x()) {
+	    soc_is_qca953x() ||
+	    soc_is_qca955x() ||
+        soc_is_qca956x()) 
+    {
 		ath79_uart_data[0].uartclk = clk_get_rate(clk);
 		platform_device_register(&ath79_uart_device);
-	} else if (soc_is_ar933x()) {
+    }
+#if (defined CONFIG_SOC_AR933X)
+    else
+    if (soc_is_ar933x ()) {
 		ar933x_uart_data.uartclk = clk_get_rate(clk);
 		platform_device_register(&ar933x_uart_device);
-	} else {
-		BUG();
-	}
+    }
+#endif
+    else {
+        BUG ();
+    }
 }
 
 void __init ath79_register_wdt(void)
@@ -109,8 +121,113 @@
 	memset(&res, 0, sizeof(res));
 
 	res.flags = IORESOURCE_MEM;
-	res.start = AR71XX_RESET_BASE + AR71XX_RESET_REG_WDOG_CTRL;
+	res.start = ATH_RESET_BASE + ATH_RESET_REG_WDOG_CTRL;
 	res.end = res.start + 0x8 - 1;
 
 	platform_device_register_simple("ath79-wdt", -1, &res, 1);
 }
+
+
+/*------------------------------------------------------------------------------------------*\
+\*------------------------------------------------------------------------------------------*/
+#include <asm/uaccess.h>
+#define M_PERFCTL_EVENT(event)          ((event) << 5)
+unsigned int clocks_at_start;
+
+void start_cntrs(unsigned int event0, unsigned int event1)
+{
+	write_c0_perfcntr0(0x00000000);
+	write_c0_perfcntr1(0x00000000);
+	/*
+	 * go...
+	 */
+	write_c0_perfctrl0(0x80000000 | M_PERFCTL_EVENT(event0) | 0xf);
+	write_c0_perfctrl1(0x00000000 | M_PERFCTL_EVENT(event1) | 0xf);
+}
+
+/*------------------------------------------------------------------------------------------*\
+\*------------------------------------------------------------------------------------------*/
+void stop_cntrs(void)
+{
+	write_c0_perfctrl0(0);
+	write_c0_perfctrl1(0);
+}
+
+/*------------------------------------------------------------------------------------------*\
+\*------------------------------------------------------------------------------------------*/
+void read_cntrs(unsigned int *c0, unsigned int *c1)
+{
+	*c0 = read_c0_perfcntr0();
+	*c1 = read_c0_perfcntr1();
+}
+
+/*------------------------------------------------------------------------------------------*\
+\*------------------------------------------------------------------------------------------*/
+static int ath_ioc_open(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+/*------------------------------------------------------------------------------------------*\
+\*------------------------------------------------------------------------------------------*/
+static ssize_t ath_ioc_read(struct file *file, char *buf, size_t count, loff_t * ppos)
+{
+#ifdef CONFIG_ATH_HS_UART
+	extern void ath_hs_uart_init(void);
+#endif /* CONFIG_ATH_HS_UART */
+
+	unsigned int c0, c1, ticks = (read_c0_count() - clocks_at_start);
+	char str[256];
+	unsigned int secs = ticks / mips_hpt_frequency;
+
+	read_cntrs(&c0, &c1);
+	stop_cntrs();
+	sprintf(str, "%d secs (%#x) event0:%#x event1:%#x", secs, ticks, c0, c1);
+	copy_to_user(buf, str, strlen(str));
+
+	return (strlen(str));
+}
+
+/*------------------------------------------------------------------------------------------*\
+\*------------------------------------------------------------------------------------------*/
+static ssize_t ath_ioc_write(struct file *file, const char *buf, size_t count,
+		 loff_t * ppos)
+{
+	int event0, event1;
+
+	sscanf(buf, "%d:%d", &event0, &event1);
+	printk("\nevent0 %d event1 %d\n", event0, event1);
+
+	clocks_at_start = read_c0_count();
+	start_cntrs(event0, event1);
+
+	return (count);
+}
+
+struct file_operations ath_ioc_fops = {
+      open:ath_ioc_open,
+      read:ath_ioc_read,
+      write:ath_ioc_write,
+};
+
+/*------------------------------------------------------------------------------------------*\
+ * General purpose ioctl i/f
+\*------------------------------------------------------------------------------------------*/
+static int __init ath_init_ioc(void) {
+
+	static int _mymajor;
+
+	_mymajor = register_chrdev(77, "ATH_GPIOC", &ath_ioc_fops);
+
+	if (_mymajor < 0) {
+		printk("Failed to register GPIOC\n");
+		return _mymajor;
+	}
+
+	printk("ATH GPIOC major %d\n", _mymajor);
+	return 0;
+}
+
+device_initcall(ath_init_ioc);
+
+