--- zzzz-none-000/linux-3.10.107/arch/mips/include/asm/bitops.h	2017-06-27 09:49:32.000000000 +0000
+++ vr9-7490-729/linux-3.10.107/arch/mips/include/asm/bitops.h	2021-11-10 11:53:53.000000000 +0000
@@ -79,12 +79,13 @@
 
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
 		__asm__ __volatile__(
-		"	.set	mips3					\n"
+		"	.set	push					\n"
+		"	.set	mips32r2					\n"
 		"1:	" __LL "%0, %1			# set_bit	\n"
 		"	or	%0, %2					\n"
 		"	" __SC	"%0, %1					\n"
 		"	beqzl	%0, 1b					\n"
-		"	.set	mips0					\n"
+		"	.set	pop					\n"
 		: "=&r" (temp), "=m" (*m)
 		: "ir" (1UL << bit), "m" (*m));
 #ifdef CONFIG_CPU_MIPSR2
@@ -101,11 +102,12 @@
 	} else if (kernel_uses_llsc) {
 		do {
 			__asm__ __volatile__(
-			"	.set	mips3				\n"
+		    "	.set	push					\n"
+		    "	.set	mips32r2					\n"
 			"	" __LL "%0, %1		# set_bit	\n"
 			"	or	%0, %2				\n"
 			"	" __SC	"%0, %1				\n"
-			"	.set	mips0				\n"
+		    "	.set	pop					\n"
 			: "=&r" (temp), "+m" (*m)
 			: "ir" (1UL << bit));
 		} while (unlikely(!temp));
@@ -131,12 +133,13 @@
 
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
 		__asm__ __volatile__(
-		"	.set	mips3					\n"
+		"	.set	push					\n"
+		"	.set	mips32r2					\n"
 		"1:	" __LL "%0, %1			# clear_bit	\n"
 		"	and	%0, %2					\n"
 		"	" __SC "%0, %1					\n"
 		"	beqzl	%0, 1b					\n"
-		"	.set	mips0					\n"
+		"	.set	pop					\n"
 		: "=&r" (temp), "+m" (*m)
 		: "ir" (~(1UL << bit)));
 #ifdef CONFIG_CPU_MIPSR2
@@ -153,11 +156,12 @@
 	} else if (kernel_uses_llsc) {
 		do {
 			__asm__ __volatile__(
-			"	.set	mips3				\n"
+		    "	.set	push					\n"
+		    "	.set	mips32r2					\n"
 			"	" __LL "%0, %1		# clear_bit	\n"
 			"	and	%0, %2				\n"
 			"	" __SC "%0, %1				\n"
-			"	.set	mips0				\n"
+		    "	.set	pop					\n"
 			: "=&r" (temp), "+m" (*m)
 			: "ir" (~(1UL << bit)));
 		} while (unlikely(!temp));
@@ -197,12 +201,13 @@
 		unsigned long temp;
 
 		__asm__ __volatile__(
-		"	.set	mips3				\n"
+        "	.set	push					\n"
+        "	.set	mips32r2					\n"
 		"1:	" __LL "%0, %1		# change_bit	\n"
 		"	xor	%0, %2				\n"
 		"	" __SC	"%0, %1				\n"
 		"	beqzl	%0, 1b				\n"
-		"	.set	mips0				\n"
+        "	.set	pop					\n"
 		: "=&r" (temp), "+m" (*m)
 		: "ir" (1UL << bit));
 	} else if (kernel_uses_llsc) {
@@ -211,11 +216,12 @@
 
 		do {
 			__asm__ __volatile__(
-			"	.set	mips3				\n"
+		    "	.set	push					\n"
+		    "	.set	mips32r2					\n"
 			"	" __LL "%0, %1		# change_bit	\n"
 			"	xor	%0, %2				\n"
 			"	" __SC	"%0, %1				\n"
-			"	.set	mips0				\n"
+		    "	.set	pop					\n"
 			: "=&r" (temp), "+m" (*m)
 			: "ir" (1UL << bit));
 		} while (unlikely(!temp));
@@ -244,13 +250,14 @@
 		unsigned long temp;
 
 		__asm__ __volatile__(
-		"	.set	mips3					\n"
+        "	.set	push					\n"
+        "	.set	mips32r2					\n"
 		"1:	" __LL "%0, %1		# test_and_set_bit	\n"
 		"	or	%2, %0, %3				\n"
 		"	" __SC	"%2, %1					\n"
 		"	beqzl	%2, 1b					\n"
 		"	and	%2, %0, %3				\n"
-		"	.set	mips0					\n"
+        "	.set	pop					\n"
 		: "=&r" (temp), "+m" (*m), "=&r" (res)
 		: "r" (1UL << bit)
 		: "memory");
@@ -260,11 +267,12 @@
 
 		do {
 			__asm__ __volatile__(
-			"	.set	mips3				\n"
+		    "	.set	push					\n"
+		    "	.set	mips32r2					\n"
 			"	" __LL "%0, %1	# test_and_set_bit	\n"
 			"	or	%2, %0, %3			\n"
 			"	" __SC	"%2, %1				\n"
-			"	.set	mips0				\n"
+		    "	.set	pop					\n"
 			: "=&r" (temp), "+m" (*m), "=&r" (res)
 			: "r" (1UL << bit)
 			: "memory");
@@ -298,13 +306,14 @@
 		unsigned long temp;
 
 		__asm__ __volatile__(
-		"	.set	mips3					\n"
+        "	.set	push					\n"
+        "	.set	mips32r2					\n"
 		"1:	" __LL "%0, %1		# test_and_set_bit	\n"
 		"	or	%2, %0, %3				\n"
 		"	" __SC	"%2, %1					\n"
 		"	beqzl	%2, 1b					\n"
 		"	and	%2, %0, %3				\n"
-		"	.set	mips0					\n"
+        "	.set	pop					\n"
 		: "=&r" (temp), "+m" (*m), "=&r" (res)
 		: "r" (1UL << bit)
 		: "memory");
@@ -314,11 +323,12 @@
 
 		do {
 			__asm__ __volatile__(
-			"	.set	mips3				\n"
+		    "	.set	push					\n"
+		    "	.set	mips32r2					\n"
 			"	" __LL "%0, %1	# test_and_set_bit	\n"
 			"	or	%2, %0, %3			\n"
 			"	" __SC	"%2, %1				\n"
-			"	.set	mips0				\n"
+		    "	.set	pop					\n"
 			: "=&r" (temp), "+m" (*m), "=&r" (res)
 			: "r" (1UL << bit)
 			: "memory");
@@ -353,14 +363,15 @@
 		unsigned long temp;
 
 		__asm__ __volatile__(
-		"	.set	mips3					\n"
+        "	.set	push					\n"
+        "	.set	mips32r2					\n"
 		"1:	" __LL	"%0, %1		# test_and_clear_bit	\n"
 		"	or	%2, %0, %3				\n"
 		"	xor	%2, %3					\n"
 		"	" __SC	"%2, %1					\n"
 		"	beqzl	%2, 1b					\n"
 		"	and	%2, %0, %3				\n"
-		"	.set	mips0					\n"
+        "	.set	pop					\n"
 		: "=&r" (temp), "+m" (*m), "=&r" (res)
 		: "r" (1UL << bit)
 		: "memory");
@@ -386,12 +397,13 @@
 
 		do {
 			__asm__ __volatile__(
-			"	.set	mips3				\n"
+		    "	.set	push					\n"
+		    "	.set	mips32r2					\n"
 			"	" __LL	"%0, %1 # test_and_clear_bit	\n"
 			"	or	%2, %0, %3			\n"
 			"	xor	%2, %3				\n"
 			"	" __SC	"%2, %1				\n"
-			"	.set	mips0				\n"
+		    "	.set	pop					\n"
 			: "=&r" (temp), "+m" (*m), "=&r" (res)
 			: "r" (1UL << bit)
 			: "memory");
@@ -427,13 +439,14 @@
 		unsigned long temp;
 
 		__asm__ __volatile__(
-		"	.set	mips3					\n"
+        "	.set	push					\n"
+        "	.set	mips32r2					\n"
 		"1:	" __LL	"%0, %1		# test_and_change_bit	\n"
 		"	xor	%2, %0, %3				\n"
 		"	" __SC	"%2, %1					\n"
 		"	beqzl	%2, 1b					\n"
 		"	and	%2, %0, %3				\n"
-		"	.set	mips0					\n"
+        "	.set	pop					\n"
 		: "=&r" (temp), "+m" (*m), "=&r" (res)
 		: "r" (1UL << bit)
 		: "memory");
@@ -443,11 +456,12 @@
 
 		do {
 			__asm__ __volatile__(
-			"	.set	mips3				\n"
+		    "	.set	push					\n"
+		    "	.set	mips32r2					\n"
 			"	" __LL	"%0, %1 # test_and_change_bit	\n"
 			"	xor	%2, %0, %3			\n"
 			"	" __SC	"\t%2, %1			\n"
-			"	.set	mips0				\n"
+		    "	.set	pop					\n"
 			: "=&r" (temp), "+m" (*m), "=&r" (res)
 			: "r" (1UL << bit)
 			: "memory");
@@ -491,7 +505,7 @@
 	    __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
 		__asm__(
 		"	.set	push					\n"
-		"	.set	mips32					\n"
+		"	.set	mips32r2					\n"
 		"	clz	%0, %1					\n"
 		"	.set	pop					\n"
 		: "=r" (num)