--- zzzz-none-000/linux-3.10.107/arch/mips/include/asm/cpu.h	2017-06-27 09:49:32.000000000 +0000
+++ vr9-7490-729/linux-3.10.107/arch/mips/include/asm/cpu.h	2021-11-10 11:53:53.000000000 +0000
@@ -97,6 +97,12 @@
 #define PRID_IMP_1074K		0x9a00
 #define PRID_IMP_M14KC		0x9c00
 #define PRID_IMP_M14KEC		0x9e00
+#define PRID_IMP_INTERAPTIV_UP	0xa000
+#define PRID_IMP_INTERAPTIV_MP	0xa100
+#define PRID_IMP_PROAPTIV_UP	0xa200
+#define PRID_IMP_PROAPTIV_MP	0xa300
+#define PRID_IMP_M5150		0xa700
+#define PRID_IMP_P5600		0xa800
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -265,7 +271,7 @@
 	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
 	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
 	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
-	CPU_M14KEC,
+	CPU_M14KEC, CPU_PROAPTIV, CPU_P5600, CPU_INTERAPTIV, CPU_1074K, CPU_M5150,
 
 	/*
 	 * MIPS64 class processors
@@ -277,6 +283,7 @@
 	CPU_LAST
 };
 
+#define MIPS_FTLB_CAPABLE       0x1
 
 /*
  * ISA Level encodings
@@ -325,6 +332,11 @@
 #define MIPS_CPU_PCI		0x00400000 /* CPU has Perf Ctr Int indicator */
 #define MIPS_CPU_RIXI		0x00800000 /* CPU has TLB Read/eXec Inhibit */
 #define MIPS_CPU_MICROMIPS	0x01000000 /* CPU has microMIPS capability */
+#define MIPS_CPU_SEGMENTS       0x02000000 /* CPU supports memory segmentation */
+#define MIPS_CPU_EVA            0x04000000 /* CPU supports EVA functionality */
+#define MIPS_CPU_TLBINV         0x08000000 /* CPU supports TLBINV/F */
+#define MIPS_CPU_CM2            0x10000000 /* CPU has CM2 */
+#define MIPS_CPU_CM2_L2SYNC     0x20000000 /* CPU has CM2 L2-only SYNC feature */
 
 /*
  * CPU ASE encodings