--- zzzz-none-000/linux-3.10.107/arch/mips/include/asm/gcmpregs.h 2017-06-27 09:49:32.000000000 +0000 +++ vr9-7490-729/linux-3.10.107/arch/mips/include/asm/gcmpregs.h 2021-11-10 11:53:53.000000000 +0000 @@ -63,6 +63,10 @@ #define GCMP_GCB_GCSRAP_CMACCESS_SHF 0 #define GCMP_GCB_GCSRAP_CMACCESS_MSK GCMPGCBMSK(GCSRAP_CMACCESS, 8) #define GCMP_GCB_GCMPREV_OFS 0x0030 /* GCMP Revision Register */ +#define GCMP_GCB_GCMPREV_MAJOR_SHF 8 +#define GCMP_GCB_GCMPREV_MAJOR_MSK GCMPGCBMSK(GCMPREV_MAJOR, 8) +#define GCMP_GCB_GCMPREV_MINOR_SHF 0 +#define GCMP_GCB_GCMPREV_MINOR_MSK GCMPGCBMSK(GCMPREV_MINOR, 8) #define GCMP_GCB_GCMEM_OFS 0x0040 /* Global CM Error Mask */ #define GCMP_GCB_GCMEC_OFS 0x0048 /* Global CM Error Cause */ #define GCMP_GCB_GMEC_ERROR_TYPE_SHF 27 @@ -73,11 +77,19 @@ #define GCMP_GCB_GCMEO_OFS 0x0058 /* Global CM Error Multiple */ #define GCMP_GCB_GMEO_ERROR_2ND_SHF 0 #define GCMP_GCB_GMEO_ERROR_2ND_MSK GCMPGCBMSK(GMEO_ERROR_2ND, 5) -#define GCMP_GCB_GICBA_OFS 0x0080 /* Global Interrupt Controller Base Address */ +#define GCMP_GCB_GCMCUS_OFS 0x0060 /* GCR Custom Base */ +#define GCMP_GCB_GCMCST_OFS 0x0068 /* GCR Custom Status */ +#define GCMP_GCB_GCML2S_OFS 0x0070 /* Global L2 only Sync Register */ +#define GCMP_GCB_GICBA_OFS 0x0080 /* Global Interrupt Controller Base Address */ #define GCMP_GCB_GICBA_BASE_SHF 17 #define GCMP_GCB_GICBA_BASE_MSK GCMPGCBMSK(GICBA_BASE, 15) #define GCMP_GCB_GICBA_EN_SHF 0 #define GCMP_GCB_GICBA_EN_MSK GCMPGCBMSK(GICBA_EN, 1) +#define GCMP_GCB_CPCBA_OFS 0x0088 /* CPC Base Address */ +#define GCMP_GCB_CPCBA_BASE_SHF 15 +#define GCMP_GCB_CPCBA_BASE_MSK GCMPGCBMSK(CPCBA_BASE, 17) +#define GCMP_GCB_CPCBA_EN_SHF 0 +#define GCMP_GCB_CPCBA_EN_MSK GCMPGCBMSK(CPCBA_EN, 1) /* GCB Regions */ #define GCMP_GCB_CMxBASE_OFS(n) (0x0090+16*(n)) /* Global Region[0-3] Base Address */ @@ -93,6 +105,13 @@ #define GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2 #define GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3 +/* GCB registers */ +#define GCMP_GCB_GICST_OFS 0x00d0 /* GIC status */ +#define GCMP_GCB_GICST_EX_SHF 0 +#define GCMP_GCB_GICST_EX_MSK GCMPGCBMSK(GICST_EX, 1) +#define GCMP_GCB_CPCST_OFS 0x00f0 /* CPC status */ +#define GCMP_GCB_CPCST_EX_SHF 0 +#define GCMP_GCB_CPCST_EX_MSK GCMPGCBMSK(CPCST_EX, 1) /* Core local/Core other control block registers */ #define GCMP_CCB_RESETR_OFS 0x0000 /* Reset Release */ @@ -115,6 +134,11 @@ #define GCMP_CCB_RESETBASE_OFS 0x0020 /* Reset Exception Base */ #define GCMP_CCB_RESETBASE_BEV_SHF 12 #define GCMP_CCB_RESETBASE_BEV_MSK GCMPCCBMSK(RESETBASE_BEV, 20) +#define GCMP_CCB_RESETBASEEXT_OFS 0x0030 /* Reset Exception Base Extention */ +#define GCMP_CCB_RESETEXTBASE_BEV_SHF 20 +#define GCMP_CCB_RESETEXTBASE_BEV_MASK_MSK GCMPCCBMSK(RESETEXTBASE_BEV, 8) +#define GCMP_CCB_RESETEXTBASE_LOWBITS_SHF 0 +#define GCMP_CCB_RESETEXTBASE_BEV_MASK_LOWBITS GCMPCCBMSK(RESETEXTBASE_LOWBITS, 20) #define GCMP_CCB_ID_OFS 0x0028 /* Identification */ #define GCMP_CCB_DINTGROUP_OFS 0x0030 /* DINT Group Participate */ #define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */ @@ -122,4 +146,7 @@ extern int __init gcmp_probe(unsigned long, unsigned long); extern int __init gcmp_niocu(void); extern void __init gcmp_setregion(int, unsigned long, unsigned long, int); +extern unsigned long _gcmp_base; +#define GCMP_L2SYNC_OFFSET 0x8000 + #endif /* _ASM_GCMPREGS_H */