--- zzzz-none-000/linux-3.10.107/arch/mips/include/asm/mipsregs.h	2017-06-27 09:49:32.000000000 +0000
+++ vr9-7490-729/linux-3.10.107/arch/mips/include/asm/mipsregs.h	2021-11-10 11:53:54.000000000 +0000
@@ -140,6 +140,12 @@
  * and should be written as zero.
  */
 #define FPU_CSR_RSVD	0x001c0000
+/* ... but FPU2 uses that bits */
+#define FPU_CSR_NAN2008 0x00040000
+#define FPU_CSR_ABS2008 0x00080000
+#define FPU_CSR_MAC2008 0x00100000
+
+#define FPU_CSR_DEFAULT 0x00000000
 
 /*
  * X the exception cause indicator
@@ -413,8 +419,10 @@
 #define ST0_SR			0x00100000
 #define ST0_TS			0x00200000
 #define ST0_BEV			0x00400000
+#define ST0_MX			0x01000000
 #define ST0_RE			0x02000000
 #define ST0_FR			0x04000000
+#define _ST0_FR                 (26)
 #define ST0_CU			0xf0000000
 #define ST0_CU0			0x10000000
 #define ST0_CU1			0x20000000
@@ -568,13 +576,27 @@
 #define MIPS_CONF1_PC		(_ULCAST_(1) <<	 4)
 #define MIPS_CONF1_MD		(_ULCAST_(1) <<	 5)
 #define MIPS_CONF1_C2		(_ULCAST_(1) <<	 6)
+#define MIPS_CONF1_DA_SHF	7
+#define MIPS_CONF1_DA_SZ	3
 #define MIPS_CONF1_DA		(_ULCAST_(7) <<	 7)
+#define MIPS_CONF1_DL_SHF	10
+#define MIPS_CONF1_DL_SZ	3
 #define MIPS_CONF1_DL		(_ULCAST_(7) << 10)
+#define MIPS_CONF1_DS_SHF	13
+#define MIPS_CONF1_DS_SZ	3
 #define MIPS_CONF1_DS		(_ULCAST_(7) << 13)
+#define MIPS_CONF1_IA_SHF	16
+#define MIPS_CONF1_IA_SZ	3
 #define MIPS_CONF1_IA		(_ULCAST_(7) << 16)
+#define MIPS_CONF1_IL_SHF	19
+#define MIPS_CONF1_IL_SZ	3
 #define MIPS_CONF1_IL		(_ULCAST_(7) << 19)
+#define MIPS_CONF1_IS_SHF	22
+#define MIPS_CONF1_IS_SZ	3
 #define MIPS_CONF1_IS		(_ULCAST_(7) << 22)
-#define MIPS_CONF1_TLBS		(_ULCAST_(63)<< 25)
+#define MIPS_CONF1_TLBS_SHIFT   (25)
+#define MIPS_CONF1_TLBS_SIZE    (6)
+#define MIPS_CONF1_TLBS         (_ULCAST_(63)<< MIPS_CONF1_TLBS_SHIFT)
 
 #define MIPS_CONF2_SA		(_ULCAST_(15)<<	 0)
 #define MIPS_CONF2_SL		(_ULCAST_(15)<<	 4)
@@ -588,28 +610,72 @@
 #define MIPS_CONF3_TL		(_ULCAST_(1) <<	 0)
 #define MIPS_CONF3_SM		(_ULCAST_(1) <<	 1)
 #define MIPS_CONF3_MT		(_ULCAST_(1) <<	 2)
+#define MIPS_CONF3_CDMM		(_ULCAST_(1) <<	 3)
 #define MIPS_CONF3_SP		(_ULCAST_(1) <<	 4)
 #define MIPS_CONF3_VINT		(_ULCAST_(1) <<	 5)
 #define MIPS_CONF3_VEIC		(_ULCAST_(1) <<	 6)
 #define MIPS_CONF3_LPA		(_ULCAST_(1) <<	 7)
+#define MIPS_CONF3_ITL		(_ULCAST_(1) <<	 8)
+#define MIPS_CONF3_CTXTC	(_ULCAST_(1) <<	 9)
 #define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)
 #define MIPS_CONF3_DSP2P	(_ULCAST_(1) << 11)
 #define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)
 #define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)
 #define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)
-#define MIPS_CONF3_ISA_OE	(_ULCAST_(3) << 16)
+#define MIPS_CONF3_ISA_OE	(_ULCAST_(1) << 16)
+#define MIPS_CONF3_MCU		(_ULCAST_(1) << 17)
+#define MIPS_CONF3_MMAR		(_ULCAST_(7) << 18)
+#define MIPS_CONF3_IPLW		(_ULCAST_(3) << 21)
 #define MIPS_CONF3_VZ		(_ULCAST_(1) << 23)
+#define MIPS_CONF3_PW		(_ULCAST_(1) << 24)
+#define MIPS_CONF3_SC		(_ULCAST_(1) << 25)
+#define MIPS_CONF3_BI		(_ULCAST_(1) << 26)
+#define MIPS_CONF3_BP		(_ULCAST_(1) << 27)
+#define MIPS_CONF3_MSA		(_ULCAST_(1) << 28)
+#define MIPS_CONF3_CMGCR	(_ULCAST_(1) << 29)
+#define MIPS_CONF3_BPG		(_ULCAST_(1) << 30)
 
+#define MIPS_CONF4_MMUSIZEEXT_SHIFT	(0)
 #define MIPS_CONF4_MMUSIZEEXT	(_ULCAST_(255) << 0)
+#define MIPS_CONF4_FTLBSETS_SHIFT	(0)
+#define MIPS_CONF4_FTLBSETS	(_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
+#define MIPS_CONF4_FTLBWAYS_SHIFT	(4)
+#define MIPS_CONF4_FTLBWAYS	(_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
+#define MIPS_CONF4_FTLBPAGESIZE_SHIFT	(8)
+#define MIPS_CONF4_FTLBPAGESIZE	(_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 #define MIPS_CONF4_MMUEXTDEF	(_ULCAST_(3) << 14)
 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 
+#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT	(_ULCAST_(2) << 14)
+#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT	(_ULCAST_(3) << 14)
+#define MIPS_CONF4_KSCREXIST	(_ULCAST_(255) << 16)
+#define MIPS_CONF4_VTLBSIZEEXT_SHIFT	(24)
+#define MIPS_CONF4_VTLBSIZEEXT	(_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
+#define MIPS_CONF4_AE		(_ULCAST_(1) << 28)
+#define MIPS_CONF4_IE		(_ULCAST_(3) << 29)
+#define MIPS_CONF4_TLBINV	(_ULCAST_(2) << 29)
+
+#define MIPS_CONF5_EVA		(_ULCAST_(1) << 28)
+#define MIPS_CONF5_CV		(_ULCAST_(1) << 29)
+#define MIPS_CONF5_K		(_ULCAST_(1) << 30)
+
+#define MIPS_CONF6_JRCD		(_ULCAST_(1) << 0)
+#define MIPS_CONF6_JRCP		(_ULCAST_(1) << 1)
 #define MIPS_CONF6_SYND		(_ULCAST_(1) << 13)
+#define MIPS_CONF6_SPCD		(_ULCAST_(1) << 14)
+#define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 
 #define MIPS_CONF7_WII		(_ULCAST_(1) << 31)
-
+#define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
+#define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
 #define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)
 
+/* CMGCRBase bit definitions */
+#define MIPS_CMGCRB_BASE	11
+#define MIPS_CMGCRF_BASE	(~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
+
+/*  EntryHI bit definition */
+#define MIPS_EHINV		(_ULCAST_(1) << 10)
 
 /*
  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
@@ -621,6 +687,32 @@
 #define MIPS_FPIR_W		(_ULCAST_(1) << 20)
 #define MIPS_FPIR_L		(_ULCAST_(1) << 21)
 #define MIPS_FPIR_F64		(_ULCAST_(1) << 22)
+/* additional bits in MIPS32/64 coprocessor 2 (FPU) */
+#define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
+#define MIPS_FPIR_FC            (_ULCAST_(1) << 24)
+
+/*
+ * Bits in the MIPS32 Memory Segmentation registers.
+ */
+#define MIPS_SEGCFG_PA_SHIFT	9
+#define MIPS_SEGCFG_PA		(_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
+#define MIPS_SEGCFG_AM_SHIFT	4
+#define MIPS_SEGCFG_AM		(_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
+#define MIPS_SEGCFG_EU_SHIFT	3
+#define MIPS_SEGCFG_EU		(_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
+#define MIPS_SEGCFG_C_SHIFT	0
+#define MIPS_SEGCFG_C		(_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
+
+#define MIPS_SEGCFG_UUSK	_ULCAST_(7)
+#define MIPS_SEGCFG_USK		_ULCAST_(5)
+#define MIPS_SEGCFG_MUSUK	_ULCAST_(4)
+#define MIPS_SEGCFG_MUSK	_ULCAST_(3)
+#define MIPS_SEGCFG_MSK		_ULCAST_(2)
+#define MIPS_SEGCFG_MK		_ULCAST_(1)
+#define MIPS_SEGCFG_UK		_ULCAST_(0)
+
+/* ebase register bit definition */
+#define MIPS_EBASE_WG           (_ULCAST_(1) << 11)
 
 #ifndef __ASSEMBLY__
 
@@ -700,7 +792,7 @@
 			: "=r" (__res));				\
 	else								\
 		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
+			".set\tmips32r2\n\t"				\
 			"mfc0\t%0, " #source ", " #sel "\n\t"		\
 			".set\tmips0\n\t"				\
 			: "=r" (__res));				\
@@ -713,7 +805,7 @@
 		__res = __read_64bit_c0_split(source, sel);		\
 	else if (sel == 0)						\
 		__asm__ __volatile__(					\
-			".set\tmips3\n\t"				\
+			".set\tmips32r2\n\t"				\
 			"dmfc0\t%0, " #source "\n\t"			\
 			".set\tmips0"					\
 			: "=r" (__res));				\
@@ -734,7 +826,7 @@
 			: : "Jr" ((unsigned int)(value)));		\
 	else								\
 		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
+			".set\tmips32r2\n\t"				\
 			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
 			".set\tmips0"					\
 			: : "Jr" ((unsigned int)(value)));		\
@@ -746,7 +838,7 @@
 		__write_64bit_c0_split(register, sel, value);		\
 	else if (sel == 0)						\
 		__asm__ __volatile__(					\
-			".set\tmips3\n\t"				\
+			".set\tmips32r2\n\t"				\
 			"dmtc0\t%z0, " #register "\n\t"			\
 			".set\tmips0"					\
 			: : "Jr" (value));				\
@@ -880,6 +972,19 @@
 #define read_c0_wired()		__read_32bit_c0_register($6, 0)
 #define write_c0_wired(val)	__write_32bit_c0_register($6, 0, val)
 
+#if defined(CONFIG_CPU_MIPS_34K)
+#define read_c0_srsconf0()   __read_32bit_c0_register($6, 1)
+#define write_c0_srsconf0(val) __write_32bit_c0_register($6, 1, val)
+#define read_c0_srsconf1()   __read_32bit_c0_register($6, 2)
+#define write_c0_srsconf1(val) __write_32bit_c0_register($6, 2, val)
+#define read_c0_srsconf2()   __read_32bit_c0_register($6, 3)
+#define write_c0_srsconf2(val) __write_32bit_c0_register($6, 3, val)
+#define read_c0_srsconf3()   __read_32bit_c0_register($6, 4)
+#define write_c0_srsconf3(val) __write_32bit_c0_register($6, 4, val)
+#define read_c0_srsconf4()   __read_32bit_c0_register($6, 5)
+#define write_c0_srsconf4(val) __write_32bit_c0_register($6, 5, val)
+#endif /*--- #if defined(CONFIG_CPU_MIPS_34K) ---*/
+
 #define read_c0_info()		__read_32bit_c0_register($7, 0)
 
 #define read_c0_cache()		__read_32bit_c0_register($7, 0) /* TX39xx */
@@ -931,6 +1036,7 @@
 #define write_c0_epc(val)	__write_ulong_c0_register($14, 0, val)
 
 #define read_c0_prid()		__read_32bit_c0_register($15, 0)
+#define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
 
 #define read_c0_config()	__read_32bit_c0_register($16, 0)
 #define read_c0_config1()	__read_32bit_c0_register($16, 1)
@@ -1096,6 +1202,15 @@
 #define read_c0_ebase()		__read_32bit_c0_register($15, 1)
 #define write_c0_ebase(val)	__write_32bit_c0_register($15, 1, val)
 
+/* MIPSR3 */
+#define read_c0_segctl0()	__read_32bit_c0_register($5, 2)
+#define write_c0_segctl0(val)	__write_32bit_c0_register($5, 2, val)
+
+#define read_c0_segctl1()	__read_32bit_c0_register($5, 3)
+#define write_c0_segctl1(val)	__write_32bit_c0_register($5, 3, val)
+
+#define read_c0_segctl2()	__read_32bit_c0_register($5, 4)
+#define write_c0_segctl2(val)	__write_32bit_c0_register($5, 4, val)
 
 /* Cavium OCTEON (cnMIPS) */
 #define read_c0_cvmcount()	__read_ulong_c0_register($9, 6)
@@ -1173,13 +1288,29 @@
 	"	.set	reorder					\n"	\
 	"	# gas fails to assemble cfc1 for some archs,	\n"	\
 	"	# like Octeon.					\n"	\
-	"	.set	mips1					\n"	\
+	"	.set	mips32r2					\n"	\
 	"	cfc1	%0,"STR(source)"			\n"	\
 	"	.set	pop					\n"	\
 	: "=r" (__res));						\
 	__res;								\
 })
 
+#define write_32bit_cp1_register(dest,value)                            \
+({									\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	reorder					\n"	\
+	"	# gas fails to assemble cfc1 for some archs,	\n"	\
+	"	# like Octeon.					\n"	\
+	"	.set	mips32r2					\n"	\
+	"       ctc1    %0,"STR(dest)"                          \n"     \
+	"	.set	pop					\n"	\
+	:: "r" (value));                                                \
+})
+
+/*
+ * Macros to access the DSP ASE registers
+ */
 #ifdef HAVE_AS_DSP
 #define rddsp(mask)							\
 ({									\
@@ -1400,6 +1531,7 @@
 									\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
+	"	.set	dsp					\n"	\
 	"	.set	noat					\n"	\
 	"	# rddsp $1, %x1					\n"	\
 	"	.hword	((0x0020067c | (%x1 << 14)) >> 16)	\n"	\
@@ -1415,6 +1547,7 @@
 do {									\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
+	"	.set	dsp					\n"	\
 	"	.set	noat					\n"	\
 	"	move	$1, %0					\n"	\
 	"	# wrdsp $1, %x1					\n"	\
@@ -1431,6 +1564,7 @@
 									\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
+	"	.set	dsp					\n"	\
 	"	.set	noat					\n"	\
 	"	.hword	0x0001					\n"	\
 	"	.hword	%x1					\n"	\
@@ -1445,6 +1579,7 @@
 do {									\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
+	"	.set	dsp					\n"	\
 	"	.set	noat					\n"	\
 	"	move	$1, %0					\n"	\
 	"	.hword	0x0001					\n"	\
@@ -1487,6 +1622,7 @@
 									\
 	__asm__ __volatile__(						\
 	"	.set	push				\n"		\
+	"	.set	dsp				\n"		\
 	"	.set	noat				\n"		\
 	"	# rddsp $1, %x1				\n"		\
 	"	.word	0x7c000cb8 | (%x1 << 16)	\n"		\
@@ -1501,6 +1637,7 @@
 do {									\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
+	"	.set	dsp					\n"	\
 	"	.set	noat					\n"	\
 	"	move	$1, %0					\n"	\
 	"	# wrdsp $1, %x1					\n"	\
@@ -1516,6 +1653,7 @@
 									\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
+	"	.set	dsp					\n"	\
 	"	.set	noat					\n"	\
 	"	.word	(0x00000810 | %1)			\n"	\
 	"	move	%0, $1					\n"	\
@@ -1529,6 +1667,7 @@
 do {									\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
+	"	.set	dsp					\n"	\
 	"	.set	noat					\n"	\
 	"	move	$1, %0					\n"	\
 	"	.word	(0x00200011 | %1)			\n"	\
@@ -1632,6 +1771,15 @@
 		".set reorder");
 }
 
+static inline void tlbinvf(void)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set noreorder\n\t"
+		".word 0x42000004\n\t"
+		".set pop");
+}
+
 /*
  * Manipulate bits in a c0 register.
  */