--- zzzz-none-000/linux-3.10.107/arch/mips/include/asm/r4kcache.h 2017-06-27 09:49:32.000000000 +0000 +++ vr9-7490-729/linux-3.10.107/arch/mips/include/asm/r4kcache.h 2021-11-10 11:53:54.000000000 +0000 @@ -16,6 +16,33 @@ #include #include #include +#include + +#if defined(CONFIG_BSS_INVAL_DETECT) +#include +#include + + +static inline int send_crashreport(void) +{ + static char *argv[] = { + "/bin/sh", "-c", "dmesg > /var/flash/crash.log; msgsend ctlmgr crashreport", + NULL + }; + + static char *envp[] = { + "HOME=/", + "TERM=linux", + "PATH=/sbin:/bin:/usr/sbin:/usr/bin", NULL + }; + + int result; + + result = call_usermodehelper(argv[0], argv, envp, UMH_NO_WAIT); + + return result; +} +#endif // CONFIG_BSS_INVAL_DETECT /* * This macro return a properly sign-extended address suitable as base address @@ -28,13 +55,15 @@ * - We need a properly sign extended address for 64-bit code. To get away * without ifdefs we let the compiler do it by a type cast. */ -#define INDEX_BASE CKSEG0 +#ifndef INDEX_BASE +#define INDEX_BASE CKSEG0 +#endif #define cache_op(op,addr) \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ - " .set mips3\n\t \n" \ + " .set mips32r2\n\t \n" \ " cache %0, %1 \n" \ " .set pop \n" \ : \ @@ -52,13 +81,22 @@ extern int mt_protiflush; extern int mt_protdflush; + +#if defined(CONFIG_AVM_ENHANCED) +#define mt_cflush_init() unsigned long tflags = 0 +#define mt_cflush_lockdown() tflags = dmt() +#define mt_cflush_release() emt(tflags) +#else +#define mt_cflush_init() extern void mt_cflush_lockdown(void); extern void mt_cflush_release(void); +#endif #define BEGIN_MT_IPROT \ unsigned long flags = 0; \ unsigned long mtflags = 0; \ - if(mt_protiflush) { \ + mt_cflush_init(); \ + if(likely(mt_protiflush)) { \ local_irq_save(flags); \ ehb(); \ mtflags = dvpe(); \ @@ -66,7 +104,7 @@ } #define END_MT_IPROT \ - if(mt_protiflush) { \ + if(likely(mt_protiflush)) { \ mt_cflush_release(); \ evpe(mtflags); \ local_irq_restore(flags); \ @@ -75,7 +113,8 @@ #define BEGIN_MT_DPROT \ unsigned long flags = 0; \ unsigned long mtflags = 0; \ - if(mt_protdflush) { \ + mt_cflush_init(); \ + if(likely(mt_protdflush)) { \ local_irq_save(flags); \ ehb(); \ mtflags = dvpe(); \ @@ -83,7 +122,7 @@ } #define END_MT_DPROT \ - if(mt_protdflush) { \ + if(likely(mt_protdflush)) { \ mt_cflush_release(); \ evpe(mtflags); \ local_irq_restore(flags); \ @@ -166,6 +205,40 @@ __iflush_epilogue } +static inline void lock_icache_line(unsigned long addr) +{ + __iflush_prologue + cache_op(Index_Store_Data_I, addr); + __iflush_epilogue +} + +static inline void lock_dcache_line(unsigned long addr) +{ +#if defined(CONFIG_BSS_INVAL_DETECT) + { + static bool __print_once = false; + + if(likely(!__print_once)){ + if(unlikely(addr < (unsigned long) &__bss_stop + && (addr + cpu_dcache_line_size()) > (unsigned long) &__bss_start)) + { + pr_emerg("[%s] dcache lock line called on BSS! addr: 0x%08lx\n", + __func__, addr); + dump_stack(); + + send_crashreport(); + __print_once = true; + } + } + } +#endif // CONFIG_BSS_INVAL_DETECT + { + __iflush_prologue + cache_op(Index_Store_Data_D, addr); + __iflush_epilogue + } +} + static inline void flush_dcache_line(unsigned long addr) { __dflush_prologue @@ -175,14 +248,54 @@ static inline void invalidate_dcache_line(unsigned long addr) { - __dflush_prologue - cache_op(Hit_Invalidate_D, addr); - __dflush_epilogue +#if defined(CONFIG_BSS_INVAL_DETECT) + { + static bool __print_once = false; + + if(likely(!__print_once)){ + if(unlikely(addr < (unsigned long) &__bss_stop + && (addr + cpu_dcache_line_size()) > (unsigned long) &__bss_start)) + { + pr_emerg("[%s] dcache invalidate called on BSS! addr: 0x%08lx\n", + __func__, addr); + dump_stack(); + + send_crashreport(); + __print_once = true; + } + } + } +#endif // CONFIG_BSS_INVAL_DETECT + { + __dflush_prologue + cache_op(Hit_Invalidate_D, addr); + __dflush_epilogue + } } static inline void invalidate_scache_line(unsigned long addr) { - cache_op(Hit_Invalidate_SD, addr); +#if defined(CONFIG_BSS_INVAL_DETECT) + { + static bool __print_once = false; + + if(likely(!__print_once)){ + if(unlikely(addr < (unsigned long) &__bss_stop + && (addr + cpu_dcache_line_size()) > (unsigned long) &__bss_start)) + { + pr_emerg("[%s] sdcache invalidate called on BSS! addr: 0x%08lx\n", + __func__, addr); + dump_stack(); + + send_crashreport(); + __print_once = true; + } + } + } +#endif // CONFIG_BSS_INVAL_DETECT + { + cache_op(Hit_Invalidate_SD, addr); + } } static inline void flush_scache_line(unsigned long addr) @@ -194,7 +307,7 @@ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ - " .set mips3 \n" \ + " .set mips32r2 \n" \ "1: cache %0, (%1) \n" \ "2: .set pop \n" \ " .section __ex_table,\"a\" \n" \ @@ -203,12 +316,31 @@ : \ : "i" (op), "r" (addr)) +#ifdef CONFIG_EVA +#define protected_cachee_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set eva \n" \ + "1: cachee %0, (%1) \n" \ + "2: .set pop \n" \ + " .section __ex_table,\"a\" \n" \ + " "STR(PTR)" 1b, 2b \n" \ + " .previous" \ + : \ + : "i" (op), "r" (addr)) +#endif + /* * The next two are for badland addresses like signal trampolines. */ static inline void protected_flush_icache_line(unsigned long addr) { +#ifndef CONFIG_EVA protected_cache_op(Hit_Invalidate_I, addr); +#else + protected_cachee_op(Hit_Invalidate_I, addr); +#endif } /* @@ -219,7 +351,11 @@ */ static inline void protected_writeback_dcache_line(unsigned long addr) { +#ifndef CONFIG_EVA protected_cache_op(Hit_Writeback_Inv_D, addr); +#else + protected_cachee_op(Hit_Writeback_Inv_D, addr); +#endif } static inline void protected_writeback_scache_line(unsigned long addr) @@ -239,7 +375,7 @@ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ - " .set mips3 \n" \ + " .set mips32r2 \n" \ " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ @@ -265,7 +401,7 @@ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ - " .set mips3 \n" \ + " .set mips32r2 \n" \ " cache %1, 0x000(%0); cache %1, 0x020(%0) \n" \ " cache %1, 0x040(%0); cache %1, 0x060(%0) \n" \ " cache %1, 0x080(%0); cache %1, 0x0a0(%0) \n" \ @@ -291,7 +427,7 @@ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ - " .set mips3 \n" \ + " .set mips32r2 \n" \ " cache %1, 0x000(%0); cache %1, 0x040(%0) \n" \ " cache %1, 0x080(%0); cache %1, 0x0c0(%0) \n" \ " cache %1, 0x100(%0); cache %1, 0x140(%0) \n" \ @@ -317,7 +453,7 @@ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ - " .set mips3 \n" \ + " .set mips32r2 \n" \ " cache %1, 0x000(%0); cache %1, 0x080(%0) \n" \ " cache %1, 0x100(%0); cache %1, 0x180(%0) \n" \ " cache %1, 0x200(%0); cache %1, 0x280(%0) \n" \ @@ -339,6 +475,112 @@ : "r" (base), \ "i" (op)); +#ifdef CONFIG_EVA +#define cache16_unroll32_user(base,op) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set eva \n" \ + " cachee %1, 0x000(%0); cachee %1, 0x010(%0) \n" \ + " cachee %1, 0x020(%0); cachee %1, 0x030(%0) \n" \ + " cachee %1, 0x040(%0); cachee %1, 0x050(%0) \n" \ + " cachee %1, 0x060(%0); cachee %1, 0x070(%0) \n" \ + " cachee %1, 0x080(%0); cachee %1, 0x090(%0) \n" \ + " cachee %1, 0x0a0(%0); cachee %1, 0x0b0(%0) \n" \ + " cachee %1, 0x0c0(%0); cachee %1, 0x0d0(%0) \n" \ + " cachee %1, 0x0e0(%0); cachee %1, 0x0f0(%0) \n" \ + " cachee %1, 0x100(%0); cachee %1, 0x110(%0) \n" \ + " cachee %1, 0x120(%0); cachee %1, 0x130(%0) \n" \ + " cachee %1, 0x140(%0); cachee %1, 0x150(%0) \n" \ + " cachee %1, 0x160(%0); cachee %1, 0x170(%0) \n" \ + " cachee %1, 0x180(%0); cachee %1, 0x190(%0) \n" \ + " cachee %1, 0x1a0(%0); cachee %1, 0x1b0(%0) \n" \ + " cachee %1, 0x1c0(%0); cachee %1, 0x1d0(%0) \n" \ + " cachee %1, 0x1e0(%0); cachee %1, 0x1f0(%0) \n" \ + " .set pop \n" \ + : \ + : "r" (base), \ + "i" (op)); + +#define cache32_unroll32_user(base,op) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set eva \n" \ + " cachee %1, 0x000(%0); cachee %1, 0x020(%0) \n" \ + " cachee %1, 0x040(%0); cachee %1, 0x060(%0) \n" \ + " cachee %1, 0x080(%0); cachee %1, 0x0a0(%0) \n" \ + " cachee %1, 0x0c0(%0); cachee %1, 0x0e0(%0) \n" \ + " cachee %1, 0x100(%0); cachee %1, 0x120(%0) \n" \ + " cachee %1, 0x140(%0); cachee %1, 0x160(%0) \n" \ + " cachee %1, 0x180(%0); cachee %1, 0x1a0(%0) \n" \ + " cachee %1, 0x1c0(%0); cachee %1, 0x1e0(%0) \n" \ + " cachee %1, 0x200(%0); cachee %1, 0x220(%0) \n" \ + " cachee %1, 0x240(%0); cachee %1, 0x260(%0) \n" \ + " cachee %1, 0x280(%0); cachee %1, 0x2a0(%0) \n" \ + " cachee %1, 0x2c0(%0); cachee %1, 0x2e0(%0) \n" \ + " cachee %1, 0x300(%0); cachee %1, 0x320(%0) \n" \ + " cachee %1, 0x340(%0); cachee %1, 0x360(%0) \n" \ + " cachee %1, 0x380(%0); cachee %1, 0x3a0(%0) \n" \ + " cachee %1, 0x3c0(%0); cachee %1, 0x3e0(%0) \n" \ + " .set pop \n" \ + : \ + : "r" (base), \ + "i" (op)); + +#define cache64_unroll32_user(base,op) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set eva \n" \ + " cachee %1, 0x000(%0); cachee %1, 0x040(%0) \n" \ + " cachee %1, 0x080(%0); cachee %1, 0x0c0(%0) \n" \ + " cachee %1, 0x100(%0); cachee %1, 0x140(%0) \n" \ + " cachee %1, 0x180(%0); cachee %1, 0x1c0(%0) \n" \ + " cachee %1, 0x200(%0); cachee %1, 0x240(%0) \n" \ + " cachee %1, 0x280(%0); cachee %1, 0x2c0(%0) \n" \ + " cachee %1, 0x300(%0); cachee %1, 0x340(%0) \n" \ + " cachee %1, 0x380(%0); cachee %1, 0x3c0(%0) \n" \ + " cachee %1, 0x400(%0); cachee %1, 0x440(%0) \n" \ + " cachee %1, 0x480(%0); cachee %1, 0x4c0(%0) \n" \ + " cachee %1, 0x500(%0); cachee %1, 0x540(%0) \n" \ + " cachee %1, 0x580(%0); cachee %1, 0x5c0(%0) \n" \ + " cachee %1, 0x600(%0); cachee %1, 0x640(%0) \n" \ + " cachee %1, 0x680(%0); cachee %1, 0x6c0(%0) \n" \ + " cachee %1, 0x700(%0); cachee %1, 0x740(%0) \n" \ + " cachee %1, 0x780(%0); cachee %1, 0x7c0(%0) \n" \ + " .set pop \n" \ + : \ + : "r" (base), \ + "i" (op)); + +#define cache128_unroll32_user(base,op) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set eva \n" \ + " cachee %1, 0x000(%0); cachee %1, 0x080(%0) \n" \ + " cachee %1, 0x100(%0); cachee %1, 0x180(%0) \n" \ + " cachee %1, 0x200(%0); cachee %1, 0x280(%0) \n" \ + " cachee %1, 0x300(%0); cachee %1, 0x380(%0) \n" \ + " cachee %1, 0x400(%0); cachee %1, 0x480(%0) \n" \ + " cachee %1, 0x500(%0); cachee %1, 0x580(%0) \n" \ + " cachee %1, 0x600(%0); cachee %1, 0x680(%0) \n" \ + " cachee %1, 0x700(%0); cachee %1, 0x780(%0) \n" \ + " cachee %1, 0x800(%0); cachee %1, 0x880(%0) \n" \ + " cachee %1, 0x900(%0); cachee %1, 0x980(%0) \n" \ + " cachee %1, 0xa00(%0); cachee %1, 0xa80(%0) \n" \ + " cachee %1, 0xb00(%0); cachee %1, 0xb80(%0) \n" \ + " cachee %1, 0xc00(%0); cachee %1, 0xc80(%0) \n" \ + " cachee %1, 0xd00(%0); cachee %1, 0xd80(%0) \n" \ + " cachee %1, 0xe00(%0); cachee %1, 0xe80(%0) \n" \ + " cachee %1, 0xf00(%0); cachee %1, 0xf80(%0) \n" \ + " .set pop \n" \ + : \ + : "r" (base), \ + "i" (op)); +#endif + /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */ #define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \ static inline void blast_##pfx##cache##lsize(void) \ @@ -404,13 +646,183 @@ __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64) __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) -__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16) -__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32) __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16) __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32) __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64) __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128) +#if !defined(CONFIG_BSS_INVAL_DETECT) +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16) +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32) +#else +static inline void blast_inv_dcache16(void) +{ + unsigned long start = INDEX_BASE; + unsigned long end = start + current_cpu_data.dcache.waysize; + unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; + unsigned long ws_end = current_cpu_data.dcache.ways << + current_cpu_data.dcache.waybit; + unsigned long ws, addr; + + __inv_dflush_prologue + + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 16 * 32) + cache16_unroll32(addr|ws, Index_Writeback_Inv_D); + + __inv_dflush_epilogue +} + +static inline void blast_inv_dcache16_page(unsigned long page) +{ + unsigned long start = page; + unsigned long end = page + PAGE_SIZE; + { + static bool __print_once = false; + + if(likely(!__print_once)){ + if(unlikely(start < (unsigned long) &__bss_stop + && (start + end) > (unsigned long) &__bss_start)) + { + pr_emerg("[%s] dcache invalidate called on BSS! addr: 0x%08lx\n", + __func__, start); + dump_stack(); + + send_crashreport(); + __print_once = true; + } + } + } + + { + __inv_dflush_prologue + + do { + cache16_unroll32(start, Hit_Invalidate_D); + start += 16 * 32; + } while (start < end); + + __inv_dflush_epilogue + } +} + +static inline void blast_inv_dcache16_page_indexed(unsigned long page) +{ + unsigned long indexmask = current_cpu_data.dcache.waysize - 1; + unsigned long start = INDEX_BASE + (page & indexmask); + unsigned long end = start + PAGE_SIZE; + unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; + unsigned long ws_end = current_cpu_data.dcache.ways << + current_cpu_data.dcache.waybit; + unsigned long ws, addr; + + __inv_dflush_prologue + + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 16 * 32) + cache16_unroll32(addr|ws, Index_Writeback_Inv_D); + + __inv_dflush_epilogue +} + +static inline void blast_inv_dcache32(void) +{ + unsigned long start = INDEX_BASE; + unsigned long end = start + current_cpu_data.dcache.waysize; + unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; + unsigned long ws_end = current_cpu_data.dcache.ways << + current_cpu_data.dcache.waybit; + unsigned long ws, addr; + + __inv_dflush_prologue + + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 32 * 32) + cache32_unroll32(addr|ws, Index_Writeback_Inv_D); + + __inv_dflush_epilogue +} + +static inline void blast_inv_dcache32_page(unsigned long page) +{ + unsigned long start = page; + unsigned long end = page + PAGE_SIZE; + { + static bool __print_once = false; + + if(likely(!__print_once)){ + if(unlikely(start < (unsigned long) &__bss_stop + && (start + end) > (unsigned long) &__bss_start)) + { + pr_emerg("[%s] dcache invalidate called on BSS! addr: 0x%08lx\n", + __func__, start); + dump_stack(); + + send_crashreport(); + __print_once = true; + } + } + } + + { + __inv_dflush_prologue + + do { + cache32_unroll32(start, Hit_Invalidate_D); + start += 32 * 32; + } while (start < end); + + __inv_dflush_epilogue + } +} + +static inline void blast_inv_dcache32_page_indexed(unsigned long page) +{ + unsigned long indexmask = current_cpu_data.dcache.waysize - 1; + unsigned long start = INDEX_BASE + (page & indexmask); + unsigned long end = start + PAGE_SIZE; + unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; + unsigned long ws_end = current_cpu_data.dcache.ways << + current_cpu_data.dcache.waybit; + unsigned long ws, addr; + + __inv_dflush_prologue + + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 32 * 32) + cache32_unroll32(addr|ws, Index_Writeback_Inv_D); + + __inv_dflush_epilogue +} +#endif // !defined(CONFIG_BSS_INVAL_DETECT) + +#ifdef CONFIG_EVA + +#define __BUILD_BLAST_USER_CACHE(pfx, dcache, indexop, hitop, lsize) \ +static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \ +{ \ + unsigned long start = page; \ + unsigned long end = page + PAGE_SIZE; \ + \ + __##pfx##flush_prologue \ + \ + do { \ + cache##lsize##_unroll32_user(start, hitop); \ + start += lsize * 32; \ + } while (start < end); \ + \ + __##pfx##flush_epilogue \ +} + +__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16) +__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16) +__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32) +__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) +__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64) +__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) + +#endif + /* build blast_xxx_range, protected_blast_xxx_range */ #define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ @@ -423,7 +835,7 @@ __##pfx##flush_prologue \ \ while (1) { \ - prot##cache_op(hitop, addr); \ + prot##cache_op(hitop, addr); \ if (addr == aend) \ break; \ addr += lsize; \ @@ -432,13 +844,99 @@ __##pfx##flush_epilogue \ } +#ifndef CONFIG_EVA + __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_) -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_) __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_) + +#else + +#define __BUILD_PROT_BLAST_CACHE_RANGE(pfx, desc, hitop) \ +static inline void protected_blast_##pfx##cache##_range(unsigned long start, \ + unsigned long end) \ +{ \ + unsigned long lsize = cpu_##desc##_line_size(); \ + unsigned long addr = start & ~(lsize - 1); \ + unsigned long aend = (end - 1) & ~(lsize - 1); \ + \ + __##pfx##flush_prologue \ + \ + if (segment_eq(get_fs(), USER_DS)) \ + while (1) { \ + protected_cachee_op(hitop, addr); \ + if (addr == aend) \ + break; \ + addr += lsize; \ + } \ + else \ + while (1) { \ + protected_cache_op(hitop, addr); \ + if (addr == aend) \ + break; \ + addr += lsize; \ + } \ + \ + __##pfx##flush_epilogue \ +} + +__BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D) +__BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I) + +#endif + +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_) __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, ) +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, ) __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, ) /* blast_inv_dcache_range */ +#if !defined(CONFIG_BSS_INVAL_DETECT) __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, ) +#else +static inline void blast_inv_dcache_range(unsigned long start, unsigned long end) +{ + unsigned long lsize = cpu_dcache_line_size(); + unsigned long addr = start & ~(lsize - 1); + unsigned long aend = (end - 1) & ~(lsize - 1); + + { + static bool __print_once = false; + + if(likely(!__print_once)){ + + if(unlikely(addr < (unsigned long) &__bss_stop + && end > (unsigned long) &__bss_start)) + { + pr_emerg("[%s] dcache invalidate called on BSS! start: 0x%08lx end: 0x%08lx\n", + __func__, start, end); + dump_stack(); + + send_crashreport(); + __print_once = true; + } + } + } + + { + __inv_dflush_prologue + + while (1) { + cache_op(Hit_Invalidate_D, addr); + if (addr == aend) + break; + + addr += lsize; + } + + __inv_dflush_epilogue \ + } +} +#endif // CONFIG_BSS_INVAL_DETECT + __BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, ) +#if defined(CONFIG_AVM_ENHANCED) +#undef mt_cflush_init +#undef mt_cflush_lockdown +#undef mt_cflush_release +#endif #endif /* _ASM_R4KCACHE_H */