--- zzzz-none-000/linux-3.10.107/arch/mips/include/asm/stackframe.h 2017-06-27 09:49:32.000000000 +0000 +++ vr9-7490-729/linux-3.10.107/arch/mips/include/asm/stackframe.h 2021-11-10 11:53:54.000000000 +0000 @@ -51,6 +51,25 @@ LONG_S v1, PT_ACX(sp) #else mfhi v1 + LONG_S v1, PT_HI(sp) + mflo v1 + LONG_S v1, PT_LO(sp) +#ifdef __mips_dsp + rddsp v1 + LONG_S v1, PT_DSPCTRL(sp) + mfhi v1, $ac1 + LONG_S v1, PT_AC1HI(sp) + mflo v1, $ac1 + LONG_S v1, PT_AC1LO(sp) + mfhi v1, $ac2 + LONG_S v1, PT_AC2HI(sp) + mflo v1, $ac2 + LONG_S v1, PT_AC2LO(sp) + mfhi v1, $ac3 + LONG_S v1, PT_AC3HI(sp) + mflo v1, $ac3 + LONG_S v1, PT_AC3LO(sp) +#endif /* __mips_dsp */ #endif #ifdef CONFIG_32BIT LONG_S $8, PT_R8(sp) @@ -59,17 +78,10 @@ LONG_S $10, PT_R10(sp) LONG_S $11, PT_R11(sp) LONG_S $12, PT_R12(sp) -#ifndef CONFIG_CPU_HAS_SMARTMIPS - LONG_S v1, PT_HI(sp) - mflo v1 -#endif LONG_S $13, PT_R13(sp) LONG_S $14, PT_R14(sp) LONG_S $15, PT_R15(sp) LONG_S $24, PT_R24(sp) -#ifndef CONFIG_CPU_HAS_SMARTMIPS - LONG_S v1, PT_LO(sp) -#endif .endm .macro SAVE_STATIC @@ -195,9 +207,9 @@ * Ideally, these instructions would be shuffled in * to cover the pipeline delay. */ - .set mips32 +/* .set mips32 CPUs die SMTC können benötigen das hier nicht */ mfc0 k0, CP0_TCSTATUS - .set mips0 +/* .set mips0 */ LONG_S k0, PT_TCSTATUS(sp) #endif /* CONFIG_MIPS_MT_SMTC */ LONG_S $4, PT_R4(sp) @@ -260,6 +272,22 @@ mtlo $24 LONG_L $24, PT_HI(sp) mthi $24 +#ifdef __mips_dsp + LONG_L $24, PT_DSPCTRL(sp) + wrdsp $24 + LONG_L $24, PT_AC1LO(sp) + mtlo $24, $ac1 + LONG_L $24, PT_AC1HI(sp) + mthi $24, $ac1 + LONG_L $24, PT_AC2LO(sp) + mtlo $24, $ac2 + LONG_L $24, PT_AC2HI(sp) + mthi $24, $ac2 + LONG_L $24, PT_AC3LO(sp) + mtlo $24, $ac3 + LONG_L $24, PT_AC3HI(sp) + mthi $24, $ac3 +#endif /* __mips_dsp */ #endif #ifdef CONFIG_32BIT LONG_L $8, PT_R8(sp) @@ -448,7 +476,7 @@ .macro RESTORE_SP_AND_RET LONG_L sp, PT_R29(sp) - .set mips3 + .set mips32r2 eret .set mips0 .endm