--- zzzz-none-000/linux-3.10.107/arch/mips/include/uapi/asm/inst.h	2017-06-27 09:49:32.000000000 +0000
+++ vr9-7490-729/linux-3.10.107/arch/mips/include/uapi/asm/inst.h	2021-11-10 11:53:54.000000000 +0000
@@ -74,8 +74,16 @@
 	ext_op, dextm_op, dextu_op, dext_op,
 	ins_op, dinsm_op, dinsu_op, dins_op,
 	lx_op = 0x0a,
-	bshfl_op = 0x20,
+	lwle_op = 0x19,
+	lwre_op = 0x1a, cachee_op = 0x1b,
+	sbe_op = 0x1c, she_op = 0x1d,
+	sce_op = 0x1e, swe_op = 0x1f,
+	bshfl_op = 0x20, swle_op = 0x21,
+	swre_op = 0x22, prefe_op = 0x23,
 	dbshfl_op = 0x24,
+	lbue_op = 0x28, lhue_op = 0x29,
+	lbe_op = 0x2c, lhe_op = 0x2d,
+	lle_op = 0x2e, lwe_op = 0x2f,
 	rdhwr_op = 0x3b
 };
 
@@ -98,9 +106,11 @@
  */
 enum cop_op {
 	mfc_op	      = 0x00, dmfc_op	    = 0x01,
-	cfc_op	      = 0x02, mtc_op	    = 0x04,
-	dmtc_op	      = 0x05, ctc_op	    = 0x06,
-	bc_op	      = 0x08, cop_op	    = 0x10,
+	cfc_op	      = 0x02, mfhc_op	    = 0x03,
+	mtc_op        = 0x04, dmtc_op	    = 0x05,
+	ctc_op	      = 0x06, mthc_op	    = 0x07,
+	bc_op	      = 0x08, mftr_op       = 0x08,
+	mttr_op	      = 0x0c, cop_op        = 0x10,
 	copm_op	      = 0x18
 };
 
@@ -117,7 +127,8 @@
 enum cop0_coi_func {
 	tlbr_op	      = 0x01, tlbwi_op	    = 0x02,
 	tlbwr_op      = 0x06, tlbp_op	    = 0x08,
-	rfe_op	      = 0x10, eret_op	    = 0x18
+	rfe_op	      = 0x10, eret_op	    = 0x18,
+	wait_op       = 0x20,
 };
 
 /*
@@ -194,6 +205,13 @@
 };
 
 /*
+ * hint/re field for jr instructions.
+ */
+enum jr_hint {
+	jr_hb_hint = 0x10,
+};
+
+/*
  * (microMIPS) Major opcodes.
  */
 enum mm_major_op {
@@ -293,7 +311,9 @@
 	mm_tlbwr_op = 0x0cd,
 	mm_jalrs_op = 0x13c,
 	mm_jalrshb_op = 0x17c,
+	mm_sync_op = 0x1ad,
 	mm_syscall_op = 0x22d,
+	mm_wait_op = 0x24d,
 	mm_eret_op = 0x3cd,
 };
 
@@ -397,8 +417,10 @@
 	mm_movt1_op = 0xa5,
 	mm_ftruncw_op = 0xac,
 	mm_fneg1_op = 0xad,
+	mm_mfhc1_op = 0xc0,
 	mm_froundl_op = 0xcc,
 	mm_fcvtd1_op = 0xcd,
+	mm_mthc1_op = 0xe0,
 	mm_froundw_op = 0xec,
 	mm_fcvts1_op = 0xed,
 };
@@ -409,10 +431,11 @@
 enum mm_16c_minor_op {
 	mm_lwm16_op = 0x04,
 	mm_swm16_op = 0x05,
-	mm_jr16_op = 0x18,
-	mm_jrc_op = 0x1a,
-	mm_jalr16_op = 0x1c,
-	mm_jalrs16_op = 0x1e,
+	mm_jr16_op = 0x0c,
+	mm_jrc_op = 0x0d,
+	mm_jalr16_op = 0x0e,
+	mm_jalrs16_op = 0x0f,
+	mm_jraddiusp_op = 0x18,
 };
 
 /*
@@ -538,6 +561,27 @@
 	;))))))
 };
 
+struct spec3_format {   /* SPEC3 */
+	BITFIELD_FIELD(unsigned int opcode : 6,
+	BITFIELD_FIELD(unsigned int rs : 5,
+	BITFIELD_FIELD(unsigned int rt : 5,
+	BITFIELD_FIELD(signed int simmediate : 9,
+	BITFIELD_FIELD(unsigned int ls_func : 7,
+	;)))))
+};
+#if defined(CONFIG_AVM_ENHANCED)
+/*--- DSP-MIPS-Instruction ---*/
+struct lx_format {	/* LX format */
+	BITFIELD_FIELD(unsigned int opcode : 6,
+	BITFIELD_FIELD(unsigned int base : 5,
+	BITFIELD_FIELD(unsigned int index : 5,
+	BITFIELD_FIELD(unsigned int rd: 5,
+	BITFIELD_FIELD(unsigned int lx_opcode : 5,
+	BITFIELD_FIELD(unsigned int sp3_opcode : 6,
+	;))))))
+};
+#endif/*--- #if defined(CONFIG_AVM_ENHANCED) ---*/
+
 struct f_format {			/* FPU register format */
 	BITFIELD_FIELD(unsigned int opcode : 6,
 	BITFIELD_FIELD(unsigned int : 1,
@@ -854,6 +898,10 @@
 	struct c_format c_format;
 	struct r_format r_format;
 	struct p_format p_format;
+	struct spec3_format spec3_format;
+#if defined(CONFIG_AVM_ENHANCED)
+    struct lx_format lx_format;
+#endif/*--- #if defined(CONFIG_AVM_ENHANCED) ---*/
 	struct f_format f_format;
 	struct ma_format ma_format;
 	struct b_format b_format;