--- zzzz-none-000/linux-3.10.107/arch/mips/kernel/asm-offsets.c	2017-06-27 09:49:32.000000000 +0000
+++ vr9-7490-729/linux-3.10.107/arch/mips/kernel/asm-offsets.c	2021-11-10 11:53:54.000000000 +0000
@@ -16,6 +16,7 @@
 #include <linux/suspend.h>
 #include <asm/ptrace.h>
 #include <asm/processor.h>
+#include <asm/smp-cps.h>
 
 #include <linux/kvm_host.h>
 
@@ -56,6 +57,15 @@
 	OFFSET(PT_R31, pt_regs, regs[31]);
 	OFFSET(PT_LO, pt_regs, lo);
 	OFFSET(PT_HI, pt_regs, hi);
+#ifdef __mips_dsp
+	OFFSET(PT_AC1LO, pt_regs, ac1lo);
+	OFFSET(PT_AC1HI, pt_regs, ac1hi);
+	OFFSET(PT_AC2LO, pt_regs, ac2lo);
+	OFFSET(PT_AC2HI, pt_regs, ac2hi);
+	OFFSET(PT_AC3LO, pt_regs, ac3lo);
+	OFFSET(PT_AC3HI, pt_regs, ac3hi);
+	OFFSET(PT_DSPCTRL, pt_regs, dspctrl);
+#endif /* __mips_dsp */
 #ifdef CONFIG_CPU_HAS_SMARTMIPS
 	OFFSET(PT_ACX, pt_regs, acx);
 #endif
@@ -63,7 +73,7 @@
 	OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
 	OFFSET(PT_STATUS, pt_regs, cp0_status);
 	OFFSET(PT_CAUSE, pt_regs, cp0_cause);
-#ifdef CONFIG_MIPS_MT_SMTC
+#if defined(CONFIG_MIPS_MT_SMTC) || defined(CONFIG_MIPS_MT_SMP)
 	OFFSET(PT_TCSTATUS, pt_regs, cp0_tcstatus);
 #endif /* CONFIG_MIPS_MT_SMTC */
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
@@ -394,3 +404,15 @@
 	OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]);
 	BLANK();
 }
+
+#ifdef CONFIG_MIPS_CPS
+void output_cps_defines(void)
+{
+	COMMENT(" MIPS CPS offsets. ");
+	OFFSET(BOOTCFG_CORE, boot_config, core);
+	OFFSET(BOOTCFG_VPE, boot_config, vpe);
+	OFFSET(BOOTCFG_PC, boot_config, pc);
+	OFFSET(BOOTCFG_SP, boot_config, sp);
+	OFFSET(BOOTCFG_GP, boot_config, gp);
+}
+#endif