--- zzzz-none-000/linux-3.10.107/arch/mips/kernel/head.S	2017-06-27 09:49:32.000000000 +0000
+++ vr9-7490-729/linux-3.10.107/arch/mips/kernel/head.S	2021-11-10 11:53:54.000000000 +0000
@@ -97,6 +97,9 @@
 	mfc0	t0, CP0_STATUS
 	or	t0, ST0_CU0|\set|0x1f|\clr
 	xor	t0, 0x1f|\clr
+#ifdef CONFIG_CPU_HAS_DSP_ASE
+	or      t0, ST0_MX
+#endif
 	mtc0	t0, CP0_STATUS
 	.set	noreorder
 	sll	zero,3				# ehb
@@ -108,7 +111,7 @@
 #ifdef CONFIG_64BIT
 	setup_c0_status ST0_KX 0
 #else
-	setup_c0_status 0 0
+	setup_c0_status ST0_MX 0
 #endif
 	.endm
 
@@ -142,9 +145,13 @@
 
 	__REF
 
+#ifdef CONFIG_EVA
+	.align  8
+#endif
+
 NESTED(kernel_entry, 16, sp)			# kernel entry point
 
-	kernel_entry_setup			# cpu specific setup
+	kernel_entry_setup                      # cpu specific setup
 
 	setup_c0_status_pri
 
@@ -152,6 +159,9 @@
 	   so we jump there.  */
 	PTR_LA	t0, 0f
 	jr	t0
+#ifdef CONFIG_EVA
+	.align  8
+#endif
 0:
 
 #ifdef CONFIG_MIPS_MT_SMTC
@@ -194,6 +204,15 @@
 	set_saved_sp	sp, t0, t1
 	PTR_SUBU	sp, 4 * SZREG		# init stack pointer
 
+#ifdef CONFIG_BDI_SWITCH
+	/* Setup the PTE pointers for the Abatron bdiGDB.  */
+	la t0, 0x800002f0
+	la t1, swapper_pg_dir
+	sw t1, (t0)
+	addiu t0, 4
+	la t1, pgd_current
+	sw t1, (t0)
+#endif
 	j		start_kernel
 	END(kernel_entry)
 
@@ -204,7 +223,13 @@
  * SMP slave cpus entry point.	Board specific code for bootstrap calls this
  * function after setting up the stack and gp registers.
  */
+
+#ifdef CONFIG_EVA
+	.align  8
+#endif
+
 NESTED(smp_bootstrap, 16, sp)
+
 #ifdef CONFIG_MIPS_MT_SMTC
 	/*
 	 * Read-modify-writes of Status must be atomic, and this
@@ -225,6 +250,9 @@
 2:
 #endif /* CONFIG_MIPS_MT_SMTC */
 	j	start_secondary
+#ifdef CONFIG_EVA
+	.align  8
+#endif
 	END(smp_bootstrap)
 #endif /* CONFIG_SMP */