--- zzzz-none-000/linux-3.10.107/arch/mips/mm/sc-mips.c	2017-06-27 09:49:32.000000000 +0000
+++ vr9-7490-729/linux-3.10.107/arch/mips/mm/sc-mips.c	2021-11-10 11:53:54.000000000 +0000
@@ -7,6 +7,7 @@
 #include <linux/mm.h>
 
 #include <asm/mipsregs.h>
+#include <asm/gcmpregs.h>
 #include <asm/bcache.h>
 #include <asm/cacheops.h>
 #include <asm/page.h>
@@ -23,7 +24,11 @@
  */
 static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
 {
+	if (!cpu_has_cm2)
+		__sync();
 	blast_scache_range(addr, addr + size);
+	if (cpu_has_cm2_l2sync)
+		*(unsigned long *)(_gcmp_base + GCMP_L2SYNC_OFFSET) = 0;
 }
 
 /*
@@ -73,8 +78,12 @@
 	/* Check the bypass bit (L2B) */
 	switch (c->cputype) {
 	case CPU_34K:
-	case CPU_74K:
 	case CPU_1004K:
+	case CPU_74K:
+	case CPU_1074K:
+	case CPU_PROAPTIV:	/* proAptiv havn't L2B capability but ... */
+	case CPU_P5600:
+	case CPU_INTERAPTIV:
 	case CPU_BMIPS5000:
 		if (config2 & (1 << 12))
 			return 0;
@@ -138,6 +147,7 @@
 	if (found) {
 		mips_sc_enable();
 		bcops = &mips_sc_ops;
-	}
+	} else
+		cpu_data[0].options &= ~MIPS_CPU_CM2_L2SYNC;
 	return found;
 }