--- zzzz-none-000/linux-3.10.107/arch/mips/pci/pci-ar724x.c 2017-06-27 09:49:32.000000000 +0000 +++ vr9-7490-729/linux-3.10.107/arch/mips/pci/pci-ar724x.c 2021-11-10 11:53:54.000000000 +0000 @@ -13,10 +13,15 @@ #include #include #include +#include #include #include #include +#include +#include +#include + #define AR724X_PCI_REG_RESET 0x18 #define AR724X_PCI_REG_INT_STATUS 0x4c #define AR724X_PCI_REG_INT_MASK 0x50 @@ -30,11 +35,11 @@ #define AR7240_BAR0_WAR_VALUE 0xffff #define AR724X_PCI_CMD_INIT (PCI_COMMAND_MEMORY | \ - PCI_COMMAND_MASTER | \ - PCI_COMMAND_INVALIDATE | \ - PCI_COMMAND_PARITY | \ - PCI_COMMAND_SERR | \ - PCI_COMMAND_FAST_BACK) + PCI_COMMAND_MASTER | \ + PCI_COMMAND_INVALIDATE | \ + PCI_COMMAND_PARITY | \ + PCI_COMMAND_SERR | \ + PCI_COMMAND_FAST_BACK) struct ar724x_pci_controller { void __iomem *devcfg_base; @@ -255,14 +260,13 @@ apc = irq_get_handler_data(irq); base = apc->ctrl_base; - pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & - __raw_readl(base + AR724X_PCI_REG_INT_MASK); + pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & __raw_readl(base + AR724X_PCI_REG_INT_MASK); - if (pending & AR724X_PCI_INT_DEV0) + if (pending & AR724X_PCI_INT_DEV0) { generic_handle_irq(apc->irq_base + 0); - - else + } else { spurious_interrupt(); + } } static void ar724x_pci_irq_unmask(struct irq_data *d) @@ -279,8 +283,7 @@ switch (offset) { case 0: t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); - __raw_writel(t | AR724X_PCI_INT_DEV0, - base + AR724X_PCI_REG_INT_MASK); + __raw_writel(t | AR724X_PCI_INT_DEV0, base + AR724X_PCI_REG_INT_MASK); /* flush write */ __raw_readl(base + AR724X_PCI_REG_INT_MASK); } @@ -300,15 +303,13 @@ switch (offset) { case 0: t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); - __raw_writel(t & ~AR724X_PCI_INT_DEV0, - base + AR724X_PCI_REG_INT_MASK); + __raw_writel(t & ~AR724X_PCI_INT_DEV0, base + AR724X_PCI_REG_INT_MASK); /* flush write */ __raw_readl(base + AR724X_PCI_REG_INT_MASK); t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS); - __raw_writel(t | AR724X_PCI_INT_DEV0, - base + AR724X_PCI_REG_INT_STATUS); + __raw_writel(t | AR724X_PCI_INT_DEV0, base + AR724X_PCI_REG_INT_STATUS); /* flush write */ __raw_readl(base + AR724X_PCI_REG_INT_STATUS); @@ -322,8 +323,7 @@ .irq_mask_ack = ar724x_pci_irq_mask, }; -static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc, - int id) +static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc, int id) { void __iomem *base; int i; @@ -335,10 +335,8 @@ apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT); - for (i = apc->irq_base; - i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) { - irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, - handle_level_irq); + for (i = apc->irq_base; i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) { + irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, handle_level_irq); irq_set_chip_data(i, apc); } @@ -346,6 +344,73 @@ irq_set_chained_handler(apc->irq, ar724x_pci_irq_handler); } +static void ar724x_pci_reset(struct ar724x_pci_controller *apc) { + + int gpio_pcie_reset = 0; + + /*----------------------------------------------------------------------*\ + * Initialize PCIE PLL and get it out of RESET + * reg = 0x18050010 + \*----------------------------------------------------------------------*/ + if(avm_get_hw_config(AVM_HW_CONFIG_VERSION, "gpio_avm_pcie_reset", &gpio_pcie_reset, NULL)) { + printk("[%s] \n", __func__); + } + + /*----------------------------------------------------------------------*\ + * PCIE aus dem Reset holen + \*----------------------------------------------------------------------*/ +#if defined(CONFIG_SOC_AR724X) + ath_reg_rmw_set(ATH_RESET, RST_RESET_PCIE_PHY_SERIAL_SET(1)); + mdelay(100); +#endif + + ath_reg_rmw_set(ATH_RESET, RST_RESET_PCIE_PHY_RESET_SET(1)); + mdelay(10); + + ath_reg_rmw_set(ATH_RESET, RST_RESET_PCIE_RESET_SET(1)); + mdelay(10); + +#if ! defined(CONFIG_SOC_AR724X) + ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); + mdelay(10); + + ath_reg_wr_nf(PCIE_RESET_ADDRESS, 0); // Put endpoint in reset + if (gpio_pcie_reset) + ath_avm_gpio_out_bit(gpio_pcie_reset, 0); + mdelay(100); + + ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); + mdelay(10); +#endif + +#if defined(CONFIG_SOC_AR724X) + ath_reg_rmw_clear(ATH_RESET,RST_RESET_PCIE_PHY_SERIAL_SET(1)); + mdelay(10); +#endif + + ath_reg_rmw_clear(ATH_RESET, RST_RESET_PCIE_PHY_RESET_SET(1)); + mdelay(10); + + ath_reg_rmw_clear(ATH_RESET, RST_RESET_PCIE_RESET_SET(1)); + mdelay(10); + + ath_reg_wr_nf(PCIE_APP_ADDRESS, PCIE_APP_PCIE_BAR_MSN_SET(1) | + PCIE_APP_CFG_BE_SET(0xf) | + PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) | + PCIE_APP_LTSSM_ENABLE_SET(1)); + + + ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT); + ar724x_pci_local_write(apc, 0x20, 4, 0x1ff01000); + ar724x_pci_local_write(apc, 0x24, 4, 0x1ff01000); + + ath_reg_wr_nf(PCIE_RESET_ADDRESS, 4); + if (gpio_pcie_reset) + ath_avm_gpio_out_bit(gpio_pcie_reset, 1); + mdelay(100); + +} + static int ar724x_pci_probe(struct platform_device *pdev) { struct ar724x_pci_controller *apc; @@ -356,8 +421,7 @@ if (id == -1) id = 0; - apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller), - GFP_KERNEL); + apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller), GFP_KERNEL); if (!apc) return -ENOMEM; @@ -415,13 +479,13 @@ apc->pci_controller.io_resource = &apc->io_res; apc->pci_controller.mem_resource = &apc->mem_res; - apc->link_up = ar724x_pci_check_link(apc); - if (!apc->link_up) - dev_warn(&pdev->dev, "PCIe link is down\n"); + ar724x_pci_reset(apc); /*--- reset PCI - Hardware ---*/ ar724x_pci_irq_init(apc, id); - ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT); + apc->link_up = ar724x_pci_check_link(apc); + if (!apc->link_up) + dev_warn(&pdev->dev, "\n"); register_pci_controller(&apc->pci_controller);