/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface * * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or (at * your option) any later version. * * Thanks to the following companies for their support: * * - JMicron (hardware and technical support) */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "sdhci.h" #include "sdhci-pci.h" #include "sdhci-pci-o2micro.h" static int sdhci_pci_enable_dma(struct sdhci_host *host); static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); static void sdhci_pci_hw_reset(struct sdhci_host *host); static int sdhci_pci_select_drive_strength(struct sdhci_host *host, struct mmc_card *card, unsigned int max_dtr, int host_drv, int card_drv, int *drv_type); /*****************************************************************************\ * * * Hardware specific quirk handling * * * \*****************************************************************************/ static int ricoh_probe(struct sdhci_pci_chip *chip) { if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; return 0; } static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) { slot->host->caps = ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) & SDHCI_TIMEOUT_CLK_MASK) | ((0x21 << SDHCI_CLOCK_BASE_SHIFT) & SDHCI_CLOCK_BASE_MASK) | SDHCI_TIMEOUT_CLK_UNIT | SDHCI_CAN_VDD_330 | SDHCI_CAN_DO_HISPD | SDHCI_CAN_DO_SDMA; return 0; } static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) { /* Apply a delay to allow controller to settle */ /* Otherwise it becomes confused if card state changed during suspend */ msleep(500); return 0; } static const struct sdhci_pci_fixes sdhci_ricoh = { .probe = ricoh_probe, .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_FORCE_DMA | SDHCI_QUIRK_CLOCK_BEFORE_RESET, }; static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { .probe_slot = ricoh_mmc_probe_slot, .resume = ricoh_mmc_resume, .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_CLOCK_BEFORE_RESET | SDHCI_QUIRK_NO_CARD_NO_RESET | SDHCI_QUIRK_MISSING_CAPS }; static const struct sdhci_pci_fixes sdhci_ene_712 = { .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_BROKEN_DMA, }; static const struct sdhci_pci_fixes sdhci_ene_714 = { .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | SDHCI_QUIRK_BROKEN_DMA, }; static const struct sdhci_pci_fixes sdhci_cafe = { .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | SDHCI_QUIRK_NO_BUSY_IRQ | SDHCI_QUIRK_BROKEN_CARD_DETECTION | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, }; static const struct sdhci_pci_fixes sdhci_intel_qrk = { .quirks = SDHCI_QUIRK_NO_HISPD_BIT, }; static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) { slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; return 0; } /* * ADMA operation is disabled for Moorestown platform due to * hardware bugs. */ static int mrst_hc_probe(struct sdhci_pci_chip *chip) { /* * slots number is fixed here for MRST as SDIO3/5 are never used and * have hardware bugs. */ chip->num_slots = 1; return 0; } static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) { slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; return 0; } #ifdef CONFIG_PM static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) { struct sdhci_pci_slot *slot = dev_id; struct sdhci_host *host = slot->host; mmc_detect_change(host->mmc, msecs_to_jiffies(200)); return IRQ_HANDLED; } static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) { int err, irq, gpio = slot->cd_gpio; slot->cd_gpio = -EINVAL; slot->cd_irq = -EINVAL; if (!gpio_is_valid(gpio)) return; err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); if (err < 0) goto out; err = gpio_direction_input(gpio); if (err < 0) goto out_free; irq = gpio_to_irq(gpio); if (irq < 0) goto out_free; err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "sd_cd", slot); if (err) goto out_free; slot->cd_gpio = gpio; slot->cd_irq = irq; return; out_free: devm_gpio_free(&slot->chip->pdev->dev, gpio); out: dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); } static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) { if (slot->cd_irq >= 0) free_irq(slot->cd_irq, slot); } #else static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) { } static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) { } #endif static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) { slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | MMC_CAP2_HC_ERASE_SZ; return 0; } static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) { slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; return 0; } static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, .probe_slot = mrst_hc_probe_slot, }; static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, .probe = mrst_hc_probe, }; static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .allow_runtime_pm = true, .own_cd_for_runtime_pm = true, }; static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, .allow_runtime_pm = true, .probe_slot = mfd_sdio_probe_slot, }; static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .allow_runtime_pm = true, .probe_slot = mfd_emmc_probe_slot, }; static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { .quirks = SDHCI_QUIRK_BROKEN_ADMA, .probe_slot = pch_hc_probe_slot, }; static void sdhci_pci_int_hw_reset(struct sdhci_host *host) { u8 reg; reg = sdhci_readb(host, SDHCI_POWER_CONTROL); reg |= 0x10; sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); /* For eMMC, minimum is 1us but give it 9us for good measure */ udelay(9); reg &= ~0x10; sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); /* For eMMC, minimum is 200us but give it 300us for good measure */ usleep_range(300, 1000); } static int spt_select_drive_strength(struct sdhci_host *host, struct mmc_card *card, unsigned int max_dtr, int host_drv, int card_drv, int *drv_type) { int drive_strength; if (sdhci_pci_spt_drive_strength > 0) drive_strength = sdhci_pci_spt_drive_strength & 0xf; else drive_strength = 0; /* Default 50-ohm */ if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0) drive_strength = 0; /* Default 50-ohm */ return drive_strength; } /* Try to read the drive strength from the card */ static void spt_read_drive_strength(struct sdhci_host *host) { u32 val, i, t; u16 m; if (sdhci_pci_spt_drive_strength) return; sdhci_pci_spt_drive_strength = -1; m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7; if (m != 3 && m != 5) return; val = sdhci_readl(host, SDHCI_PRESENT_STATE); if (val & 0x3) return; sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE); sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE); sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); sdhci_writew(host, 512, SDHCI_BLOCK_SIZE); sdhci_writew(host, 1, SDHCI_BLOCK_COUNT); sdhci_writel(host, 0, SDHCI_ARGUMENT); sdhci_writew(host, 0x83b, SDHCI_COMMAND); for (i = 0; i < 1000; i++) { val = sdhci_readl(host, SDHCI_INT_STATUS); if (val & 0xffff8000) return; if (val & 0x20) break; udelay(1); } val = sdhci_readl(host, SDHCI_PRESENT_STATE); if (!(val & 0x800)) return; for (i = 0; i < 47; i++) val = sdhci_readl(host, SDHCI_BUFFER); t = val & 0xf00; if (t != 0x200 && t != 0x300) return; sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf); } static int bxt_get_cd(struct mmc_host *mmc) { int gpio_cd = mmc_gpio_get_cd(mmc); struct sdhci_host *host = mmc_priv(mmc); unsigned long flags; int ret = 0; if (!gpio_cd) return 0; spin_lock_irqsave(&host->lock, flags); if (host->flags & SDHCI_DEVICE_DEAD) goto out; ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); out: spin_unlock_irqrestore(&host->lock, flags); return ret; } static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) { slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | MMC_CAP_CMD_DURING_TFR | MMC_CAP_WAIT_WHILE_BUSY; slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; slot->hw_reset = sdhci_pci_int_hw_reset; if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) { spt_read_drive_strength(slot->host); slot->select_drive_strength = spt_select_drive_strength; } return 0; } static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) { slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | MMC_CAP_WAIT_WHILE_BUSY; return 0; } static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) { slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; slot->cd_con_id = NULL; slot->cd_idx = 0; slot->cd_override_level = true; if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD) { slot->host->mmc_host_ops.get_cd = bxt_get_cd; slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; } return 0; } #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd) { int cntr; u8 reg; sdhci_set_power(host, mode, vdd); if (mode == MMC_POWER_OFF) return; spin_unlock_irq(&host->lock); /* * Bus power might not enable after D3 -> D0 transition due to the * present state not yet having propagated. Retry for up to 2ms. */ for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { reg = sdhci_readb(host, SDHCI_POWER_CONTROL); if (reg & SDHCI_POWER_ON) break; udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); reg |= SDHCI_POWER_ON; sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); } spin_lock_irq(&host->lock); } static const struct sdhci_ops sdhci_intel_byt_ops = { .set_clock = sdhci_set_clock, .set_power = sdhci_intel_set_power, .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_pci_set_bus_width, .reset = sdhci_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, .hw_reset = sdhci_pci_hw_reset, .select_drive_strength = sdhci_pci_select_drive_strength, }; static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { .allow_runtime_pm = true, .probe_slot = byt_emmc_probe_slot, .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | SDHCI_QUIRK2_STOP_WITH_TC, .ops = &sdhci_intel_byt_ops, }; static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | SDHCI_QUIRK2_PRESET_VALUE_BROKEN, .allow_runtime_pm = true, .probe_slot = byt_sdio_probe_slot, .ops = &sdhci_intel_byt_ops, }; static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | SDHCI_QUIRK2_PRESET_VALUE_BROKEN | SDHCI_QUIRK2_STOP_WITH_TC, .allow_runtime_pm = true, .own_cd_for_runtime_pm = true, .probe_slot = byt_sd_probe_slot, .ops = &sdhci_intel_byt_ops, }; /* Define Host controllers for Intel Merrifield platform */ #define INTEL_MRFLD_EMMC_0 0 #define INTEL_MRFLD_EMMC_1 1 #define INTEL_MRFLD_SD 2 #define INTEL_MRFLD_SDIO 3 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) { unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); switch (func) { case INTEL_MRFLD_EMMC_0: case INTEL_MRFLD_EMMC_1: slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | MMC_CAP_8_BIT_DATA | MMC_CAP_1_8V_DDR; break; case INTEL_MRFLD_SD: slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; break; case INTEL_MRFLD_SDIO: /* Advertise 2.0v for compatibility with the SDIO card's OCR */ slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD; break; default: return -ENODEV; } return 0; } static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN, .allow_runtime_pm = true, .probe_slot = intel_mrfld_mmc_probe_slot, }; /* O2Micro extra registers */ #define O2_SD_LOCK_WP 0xD3 #define O2_SD_MULTI_VCC3V 0xEE #define O2_SD_CLKREQ 0xEC #define O2_SD_CAPS 0xE0 #define O2_SD_ADMA1 0xE2 #define O2_SD_ADMA2 0xE7 #define O2_SD_INF_MOD 0xF1 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) { u8 scratch; int ret; ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); if (ret) return ret; /* * Turn PMOS on [bit 0], set over current detection to 2.4 V * [bit 1:2] and enable over current debouncing [bit 6]. */ if (on) scratch |= 0x47; else scratch &= ~0x47; return pci_write_config_byte(chip->pdev, 0xAE, scratch); } static int jmicron_probe(struct sdhci_pci_chip *chip) { int ret; u16 mmcdev = 0; if (chip->pdev->revision == 0) { chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_32BIT_DMA_SIZE | SDHCI_QUIRK_32BIT_ADMA_SIZE | SDHCI_QUIRK_RESET_AFTER_REQUEST | SDHCI_QUIRK_BROKEN_SMALL_PIO; } /* * JMicron chips can have two interfaces to the same hardware * in order to work around limitations in Microsoft's driver. * We need to make sure we only bind to one of them. * * This code assumes two things: * * 1. The PCI code adds subfunctions in order. * * 2. The MMC interface has a lower subfunction number * than the SD interface. */ if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; if (mmcdev) { struct pci_dev *sd_dev; sd_dev = NULL; while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, mmcdev, sd_dev)) != NULL) { if ((PCI_SLOT(chip->pdev->devfn) == PCI_SLOT(sd_dev->devfn)) && (chip->pdev->bus == sd_dev->bus)) break; } if (sd_dev) { pci_dev_put(sd_dev); dev_info(&chip->pdev->dev, "Refusing to bind to " "secondary interface.\n"); return -ENODEV; } } /* * JMicron chips need a bit of a nudge to enable the power * output pins. */ ret = jmicron_pmos(chip, 1); if (ret) { dev_err(&chip->pdev->dev, "Failure enabling card power\n"); return ret; } /* quirk for unsable RO-detection on JM388 chips */ if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; return 0; } static void jmicron_enable_mmc(struct sdhci_host *host, int on) { u8 scratch; scratch = readb(host->ioaddr + 0xC0); if (on) scratch |= 0x01; else scratch &= ~0x01; writeb(scratch, host->ioaddr + 0xC0); } static int jmicron_probe_slot(struct sdhci_pci_slot *slot) { if (slot->chip->pdev->revision == 0) { u16 version; version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); version = (version & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT; /* * Older versions of the chip have lots of nasty glitches * in the ADMA engine. It's best just to avoid it * completely. */ if (version < 0xAC) slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; } /* JM388 MMC doesn't support 1.8V while SD supports it */ if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_165_195; /* allow 1.8V */ slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ } /* * The secondary interface requires a bit set to get the * interrupts. */ if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) jmicron_enable_mmc(slot->host, 1); slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; return 0; } static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) { if (dead) return; if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) jmicron_enable_mmc(slot->host, 0); } static int jmicron_suspend(struct sdhci_pci_chip *chip) { int i; if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { for (i = 0; i < chip->num_slots; i++) jmicron_enable_mmc(chip->slots[i]->host, 0); } return 0; } static int jmicron_resume(struct sdhci_pci_chip *chip) { int ret, i; if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { for (i = 0; i < chip->num_slots; i++) jmicron_enable_mmc(chip->slots[i]->host, 1); } ret = jmicron_pmos(chip, 1); if (ret) { dev_err(&chip->pdev->dev, "Failure enabling card power\n"); return ret; } return 0; } static const struct sdhci_pci_fixes sdhci_o2 = { .probe = sdhci_pci_o2_probe, .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, .probe_slot = sdhci_pci_o2_probe_slot, .resume = sdhci_pci_o2_resume, }; static const struct sdhci_pci_fixes sdhci_jmicron = { .probe = jmicron_probe, .probe_slot = jmicron_probe_slot, .remove_slot = jmicron_remove_slot, .suspend = jmicron_suspend, .resume = jmicron_resume, }; /* SysKonnect CardBus2SDIO extra registers */ #define SYSKT_CTRL 0x200 #define SYSKT_RDFIFO_STAT 0x204 #define SYSKT_WRFIFO_STAT 0x208 #define SYSKT_POWER_DATA 0x20c #define SYSKT_POWER_330 0xef #define SYSKT_POWER_300 0xf8 #define SYSKT_POWER_184 0xcc #define SYSKT_POWER_CMD 0x20d #define SYSKT_POWER_START (1 << 7) #define SYSKT_POWER_STATUS 0x20e #define SYSKT_POWER_STATUS_OK (1 << 0) #define SYSKT_BOARD_REV 0x210 #define SYSKT_CHIP_REV 0x211 #define SYSKT_CONF_DATA 0x212 #define SYSKT_CONF_DATA_1V8 (1 << 2) #define SYSKT_CONF_DATA_2V5 (1 << 1) #define SYSKT_CONF_DATA_3V3 (1 << 0) static int syskt_probe(struct sdhci_pci_chip *chip) { if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { chip->pdev->class &= ~0x0000FF; chip->pdev->class |= PCI_SDHCI_IFDMA; } return 0; } static int syskt_probe_slot(struct sdhci_pci_slot *slot) { int tm, ps; u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " "board rev %d.%d, chip rev %d.%d\n", board_rev >> 4, board_rev & 0xf, chip_rev >> 4, chip_rev & 0xf); if (chip_rev >= 0x20) slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); udelay(50); tm = 10; /* Wait max 1 ms */ do { ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); if (ps & SYSKT_POWER_STATUS_OK) break; udelay(100); } while (--tm); if (!tm) { dev_err(&slot->chip->pdev->dev, "power regulator never stabilized"); writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); return -ENODEV; } return 0; } static const struct sdhci_pci_fixes sdhci_syskt = { .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, .probe = syskt_probe, .probe_slot = syskt_probe_slot, }; static int via_probe(struct sdhci_pci_chip *chip) { if (chip->pdev->revision == 0x10) chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; return 0; } static const struct sdhci_pci_fixes sdhci_via = { .probe = via_probe, }; static int rtsx_probe_slot(struct sdhci_pci_slot *slot) { slot->host->mmc->caps2 |= MMC_CAP2_HS200; return 0; } static const struct sdhci_pci_fixes sdhci_rtsx = { .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | SDHCI_QUIRK2_BROKEN_64_BIT_DMA | SDHCI_QUIRK2_BROKEN_DDR50, .probe_slot = rtsx_probe_slot, }; /*AMD chipset generation*/ enum amd_chipset_gen { AMD_CHIPSET_BEFORE_ML, AMD_CHIPSET_CZ, AMD_CHIPSET_NL, AMD_CHIPSET_UNKNOWN, }; static int amd_probe(struct sdhci_pci_chip *chip) { struct pci_dev *smbus_dev; enum amd_chipset_gen gen; smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); if (smbus_dev) { gen = AMD_CHIPSET_BEFORE_ML; } else { smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); if (smbus_dev) { if (smbus_dev->revision < 0x51) gen = AMD_CHIPSET_CZ; else gen = AMD_CHIPSET_NL; } else { gen = AMD_CHIPSET_UNKNOWN; } } if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) { chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; } return 0; } static const struct sdhci_pci_fixes sdhci_amd = { .probe = amd_probe, }; static const struct pci_device_id pci_ids[] = { { .vendor = PCI_VENDOR_ID_RICOH, .device = PCI_DEVICE_ID_RICOH_R5C822, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_ricoh, }, { .vendor = PCI_VENDOR_ID_RICOH, .device = 0x843, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, }, { .vendor = PCI_VENDOR_ID_RICOH, .device = 0xe822, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, }, { .vendor = PCI_VENDOR_ID_RICOH, .device = 0xe823, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, }, { .vendor = PCI_VENDOR_ID_ENE, .device = PCI_DEVICE_ID_ENE_CB712_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_ene_712, }, { .vendor = PCI_VENDOR_ID_ENE, .device = PCI_DEVICE_ID_ENE_CB712_SD_2, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_ene_712, }, { .vendor = PCI_VENDOR_ID_ENE, .device = PCI_DEVICE_ID_ENE_CB714_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_ene_714, }, { .vendor = PCI_VENDOR_ID_ENE, .device = PCI_DEVICE_ID_ENE_CB714_SD_2, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_ene_714, }, { .vendor = PCI_VENDOR_ID_MARVELL, .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_cafe, }, { .vendor = PCI_VENDOR_ID_JMICRON, .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_jmicron, }, { .vendor = PCI_VENDOR_ID_JMICRON, .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_jmicron, }, { .vendor = PCI_VENDOR_ID_JMICRON, .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_jmicron, }, { .vendor = PCI_VENDOR_ID_JMICRON, .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_jmicron, }, { .vendor = PCI_VENDOR_ID_SYSKONNECT, .device = 0x8000, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_syskt, }, { .vendor = PCI_VENDOR_ID_VIA, .device = 0x95d0, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_via, }, { .vendor = PCI_VENDOR_ID_REALTEK, .device = 0x5250, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_rtsx, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_QRK_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MRST_SD0, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MRST_SD1, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MRST_SD2, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MFD_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_BYT_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_BSW_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_SPT_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_BXT_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_BXTM_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_APL_EMMC, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_APL_SDIO, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_APL_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, }, { .vendor = PCI_VENDOR_ID_O2, .device = PCI_DEVICE_ID_O2_8120, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_o2, }, { .vendor = PCI_VENDOR_ID_O2, .device = PCI_DEVICE_ID_O2_8220, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_o2, }, { .vendor = PCI_VENDOR_ID_O2, .device = PCI_DEVICE_ID_O2_8221, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_o2, }, { .vendor = PCI_VENDOR_ID_O2, .device = PCI_DEVICE_ID_O2_8320, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_o2, }, { .vendor = PCI_VENDOR_ID_O2, .device = PCI_DEVICE_ID_O2_8321, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_o2, }, { .vendor = PCI_VENDOR_ID_O2, .device = PCI_DEVICE_ID_O2_FUJIN2, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_o2, }, { .vendor = PCI_VENDOR_ID_O2, .device = PCI_DEVICE_ID_O2_SDS0, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_o2, }, { .vendor = PCI_VENDOR_ID_O2, .device = PCI_DEVICE_ID_O2_SDS1, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_o2, }, { .vendor = PCI_VENDOR_ID_O2, .device = PCI_DEVICE_ID_O2_SEABIRD0, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_o2, }, { .vendor = PCI_VENDOR_ID_O2, .device = PCI_DEVICE_ID_O2_SEABIRD1, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_o2, }, { .vendor = PCI_VENDOR_ID_AMD, .device = PCI_ANY_ID, .class = PCI_CLASS_SYSTEM_SDHCI << 8, .class_mask = 0xFFFF00, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_amd, }, { /* Generic SD host controller */ PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) }, { /* end: all zeroes */ }, }; MODULE_DEVICE_TABLE(pci, pci_ids); /*****************************************************************************\ * * * SDHCI core callbacks * * * \*****************************************************************************/ static int sdhci_pci_enable_dma(struct sdhci_host *host) { struct sdhci_pci_slot *slot; struct pci_dev *pdev; slot = sdhci_priv(host); pdev = slot->chip->pdev; if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && (host->flags & SDHCI_USE_SDMA)) { dev_warn(&pdev->dev, "Will use DMA mode even though HW " "doesn't fully claim to support it.\n"); } pci_set_master(pdev); return 0; } static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) { u8 ctrl; ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); switch (width) { case MMC_BUS_WIDTH_8: ctrl |= SDHCI_CTRL_8BITBUS; ctrl &= ~SDHCI_CTRL_4BITBUS; break; case MMC_BUS_WIDTH_4: ctrl |= SDHCI_CTRL_4BITBUS; ctrl &= ~SDHCI_CTRL_8BITBUS; break; default: ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); break; } sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); } static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) { struct sdhci_pci_slot *slot = sdhci_priv(host); int rst_n_gpio = slot->rst_n_gpio; if (!gpio_is_valid(rst_n_gpio)) return; gpio_set_value_cansleep(rst_n_gpio, 0); /* For eMMC, minimum is 1us but give it 10us for good measure */ udelay(10); gpio_set_value_cansleep(rst_n_gpio, 1); /* For eMMC, minimum is 200us but give it 300us for good measure */ usleep_range(300, 1000); } static void sdhci_pci_hw_reset(struct sdhci_host *host) { struct sdhci_pci_slot *slot = sdhci_priv(host); if (slot->hw_reset) slot->hw_reset(host); } static int sdhci_pci_select_drive_strength(struct sdhci_host *host, struct mmc_card *card, unsigned int max_dtr, int host_drv, int card_drv, int *drv_type) { struct sdhci_pci_slot *slot = sdhci_priv(host); if (!slot->select_drive_strength) return 0; return slot->select_drive_strength(host, card, max_dtr, host_drv, card_drv, drv_type); } static const struct sdhci_ops sdhci_pci_ops = { .set_clock = sdhci_set_clock, .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_pci_set_bus_width, .reset = sdhci_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, .hw_reset = sdhci_pci_hw_reset, .select_drive_strength = sdhci_pci_select_drive_strength, }; /*****************************************************************************\ * * * Suspend/resume * * * \*****************************************************************************/ #ifdef CONFIG_PM_SLEEP static int sdhci_pci_suspend(struct device *dev) { struct pci_dev *pdev = to_pci_dev(dev); struct sdhci_pci_chip *chip; struct sdhci_pci_slot *slot; mmc_pm_flag_t slot_pm_flags; mmc_pm_flag_t pm_flags = 0; int i, ret; chip = pci_get_drvdata(pdev); if (!chip) return 0; for (i = 0; i < chip->num_slots; i++) { slot = chip->slots[i]; if (!slot) continue; ret = sdhci_suspend_host(slot->host); if (ret) goto err_pci_suspend; slot_pm_flags = slot->host->mmc->pm_flags; if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) sdhci_enable_irq_wakeups(slot->host); pm_flags |= slot_pm_flags; } if (chip->fixes && chip->fixes->suspend) { ret = chip->fixes->suspend(chip); if (ret) goto err_pci_suspend; } if (pm_flags & MMC_PM_KEEP_POWER) { if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) device_init_wakeup(dev, true); else device_init_wakeup(dev, false); } else device_init_wakeup(dev, false); return 0; err_pci_suspend: while (--i >= 0) sdhci_resume_host(chip->slots[i]->host); return ret; } static int sdhci_pci_resume(struct device *dev) { struct pci_dev *pdev = to_pci_dev(dev); struct sdhci_pci_chip *chip; struct sdhci_pci_slot *slot; int i, ret; chip = pci_get_drvdata(pdev); if (!chip) return 0; if (chip->fixes && chip->fixes->resume) { ret = chip->fixes->resume(chip); if (ret) return ret; } for (i = 0; i < chip->num_slots; i++) { slot = chip->slots[i]; if (!slot) continue; ret = sdhci_resume_host(slot->host); if (ret) return ret; } return 0; } #endif #ifdef CONFIG_PM static int sdhci_pci_runtime_suspend(struct device *dev) { struct pci_dev *pdev = to_pci_dev(dev); struct sdhci_pci_chip *chip; struct sdhci_pci_slot *slot; int i, ret; chip = pci_get_drvdata(pdev); if (!chip) return 0; for (i = 0; i < chip->num_slots; i++) { slot = chip->slots[i]; if (!slot) continue; ret = sdhci_runtime_suspend_host(slot->host); if (ret) goto err_pci_runtime_suspend; } if (chip->fixes && chip->fixes->suspend) { ret = chip->fixes->suspend(chip); if (ret) goto err_pci_runtime_suspend; } return 0; err_pci_runtime_suspend: while (--i >= 0) sdhci_runtime_resume_host(chip->slots[i]->host); return ret; } static int sdhci_pci_runtime_resume(struct device *dev) { struct pci_dev *pdev = to_pci_dev(dev); struct sdhci_pci_chip *chip; struct sdhci_pci_slot *slot; int i, ret; chip = pci_get_drvdata(pdev); if (!chip) return 0; if (chip->fixes && chip->fixes->resume) { ret = chip->fixes->resume(chip); if (ret) return ret; } for (i = 0; i < chip->num_slots; i++) { slot = chip->slots[i]; if (!slot) continue; ret = sdhci_runtime_resume_host(slot->host); if (ret) return ret; } return 0; } #endif static const struct dev_pm_ops sdhci_pci_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, sdhci_pci_runtime_resume, NULL) }; /*****************************************************************************\ * * * Device probing/removal * * * \*****************************************************************************/ static struct sdhci_pci_slot *sdhci_pci_probe_slot( struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, int slotno) { struct sdhci_pci_slot *slot; struct sdhci_host *host; int ret, bar = first_bar + slotno; if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); return ERR_PTR(-ENODEV); } if (pci_resource_len(pdev, bar) < 0x100) { dev_err(&pdev->dev, "Invalid iomem size. You may " "experience problems.\n"); } if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); return ERR_PTR(-ENODEV); } if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); return ERR_PTR(-ENODEV); } host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); if (IS_ERR(host)) { dev_err(&pdev->dev, "cannot allocate host\n"); return ERR_CAST(host); } slot = sdhci_priv(host); slot->chip = chip; slot->host = host; slot->rst_n_gpio = -EINVAL; slot->cd_gpio = -EINVAL; slot->cd_idx = -1; /* Retrieve platform data if there is any */ if (*sdhci_pci_get_data) slot->data = sdhci_pci_get_data(pdev, slotno); if (slot->data) { if (slot->data->setup) { ret = slot->data->setup(slot->data); if (ret) { dev_err(&pdev->dev, "platform setup failed\n"); goto free; } } slot->rst_n_gpio = slot->data->rst_n_gpio; slot->cd_gpio = slot->data->cd_gpio; } host->hw_name = "PCI"; host->ops = chip->fixes && chip->fixes->ops ? chip->fixes->ops : &sdhci_pci_ops; host->quirks = chip->quirks; host->quirks2 = chip->quirks2; host->irq = pdev->irq; ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); if (ret) { dev_err(&pdev->dev, "cannot request region\n"); goto cleanup; } host->ioaddr = pcim_iomap_table(pdev)[bar]; if (chip->fixes && chip->fixes->probe_slot) { ret = chip->fixes->probe_slot(slot); if (ret) goto cleanup; } if (gpio_is_valid(slot->rst_n_gpio)) { if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { gpio_direction_output(slot->rst_n_gpio, 1); slot->host->mmc->caps |= MMC_CAP_HW_RESET; slot->hw_reset = sdhci_pci_gpio_hw_reset; } else { dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); slot->rst_n_gpio = -EINVAL; } } host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; host->mmc->slotno = slotno; host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; if (slot->cd_idx >= 0 && mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx, slot->cd_override_level, 0, NULL)) { dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); slot->cd_idx = -1; } ret = sdhci_add_host(host); if (ret) goto remove; sdhci_pci_add_own_cd(slot); /* * Check if the chip needs a separate GPIO for card detect to wake up * from runtime suspend. If it is not there, don't allow runtime PM. * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. */ if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) chip->allow_runtime_pm = false; return slot; remove: if (chip->fixes && chip->fixes->remove_slot) chip->fixes->remove_slot(slot, 0); cleanup: if (slot->data && slot->data->cleanup) slot->data->cleanup(slot->data); free: sdhci_free_host(host); return ERR_PTR(ret); } static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) { int dead; u32 scratch; sdhci_pci_remove_own_cd(slot); dead = 0; scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); if (scratch == (u32)-1) dead = 1; sdhci_remove_host(slot->host, dead); if (slot->chip->fixes && slot->chip->fixes->remove_slot) slot->chip->fixes->remove_slot(slot, dead); if (slot->data && slot->data->cleanup) slot->data->cleanup(slot->data); sdhci_free_host(slot->host); } static void sdhci_pci_runtime_pm_allow(struct device *dev) { pm_suspend_ignore_children(dev, 1); pm_runtime_set_autosuspend_delay(dev, 50); pm_runtime_use_autosuspend(dev); pm_runtime_allow(dev); /* Stay active until mmc core scans for a card */ pm_runtime_put_noidle(dev); } static void sdhci_pci_runtime_pm_forbid(struct device *dev) { pm_runtime_forbid(dev); pm_runtime_get_noresume(dev); } static int sdhci_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { struct sdhci_pci_chip *chip; struct sdhci_pci_slot *slot; u8 slots, first_bar; int ret, i; BUG_ON(pdev == NULL); BUG_ON(ent == NULL); dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); if (ret) return ret; slots = PCI_SLOT_INFO_SLOTS(slots) + 1; dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); if (slots == 0) return -ENODEV; BUG_ON(slots > MAX_SLOTS); ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); if (ret) return ret; first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; if (first_bar > 5) { dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); return -ENODEV; } ret = pcim_enable_device(pdev); if (ret) return ret; chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; chip->pdev = pdev; chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; if (chip->fixes) { chip->quirks = chip->fixes->quirks; chip->quirks2 = chip->fixes->quirks2; chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; } chip->num_slots = slots; pci_set_drvdata(pdev, chip); if (chip->fixes && chip->fixes->probe) { ret = chip->fixes->probe(chip); if (ret) return ret; } slots = chip->num_slots; /* Quirk may have changed this */ for (i = 0; i < slots; i++) { slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); if (IS_ERR(slot)) { for (i--; i >= 0; i--) sdhci_pci_remove_slot(chip->slots[i]); return PTR_ERR(slot); } chip->slots[i] = slot; } if (chip->allow_runtime_pm) sdhci_pci_runtime_pm_allow(&pdev->dev); return 0; } static void sdhci_pci_remove(struct pci_dev *pdev) { int i; struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); if (chip->allow_runtime_pm) sdhci_pci_runtime_pm_forbid(&pdev->dev); for (i = 0; i < chip->num_slots; i++) sdhci_pci_remove_slot(chip->slots[i]); } static struct pci_driver sdhci_driver = { .name = "sdhci-pci", .id_table = pci_ids, .probe = sdhci_pci_probe, .remove = sdhci_pci_remove, .driver = { .pm = &sdhci_pci_pm_ops }, }; module_pci_driver(sdhci_driver); MODULE_AUTHOR("Pierre Ossman "); MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); MODULE_LICENSE("GPL");