You do not need makefiles to build toolkit programs because source files explicitly include all required components using include statement blocks like that shown below. You will see similar blocks near the top of most programs.

#ifndef MAKEFILE 
#include "../tools/getoptv.c" 
#include "../tools/putoptv.c" 
#include "../tools/version.c" 
... 
#endif 

This mechanism has several advantages. First, the preprocessor include statements form a complete inventory of required files. Secondly, the relative pathnames help developers locate needed source files. Third, the complete program can be compiled with one gcc command, like the one shown below. This allows program compilation in environments where the GNU make program or the Atheros Makefiles are not available.

# gcc -o program program.c 

Most toolkit makefiles define the preprocessor constant MAKEFILE as a compiler option using CFLAGS= ... -DMAKEFILE .... When this constant is defined, the compiler will not include components inside an include block like that shown above and so the Makefile is responsible for compiling and linking all components. If the constant is not defined, because no Makefile was used, the compiler will merely include everything needed.